VHDL Issue Number:      0247
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Rules for others in aggregates are incomplete.
Related Issues:         None.
Relevant LRM Sections:  7.3.2
Key Words and Phrases:  aggregates, others, declared object, subtype
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1052
-----------------------
Date Submitted:         1991/10/11
Author of Submission:   Chuck Swart
Author's Affiliation:   Mentor Graphics Corporation
Author's Post Address:  8005 S.W. Boeckman Road
                        Wilsonville, OR 97070-7777
Author's Phone Number:  (503) 685-7000
Author's Fax Number:    
Author's Net Address:   chuck_swart@mentorg.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.11 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
Consider the following VHDL code:

entity BV is
    port (A: in bit; B: out bit_vector(0 to 7));
end BV;

architecture CHK of BV is
begin
  B(0 to 3) <= (others => '0');
end CHK;

In this code, is the use of OTHERS in an aggregate legal when the target is a
slice? The LRM states:

"The subtype of an array aggregate that has an OTHERS choice must be
determinable from the context."

That certainly appears to be the case here. However, the LRM then goes on
to enumerate the cases in which an OTHERS may appear. The relevant case is:

"An OTHERS may only appear ...

As a value expression in an assignment statement, where the target is a declared
object, and the subtype of the target is a constrained array subtype."

A slice is neither a declared object, nor does it have a subtype.


Proposed Resolution
-------------------
This situation is almost certainly an oversight. At least one implementation
already supports this use of OTHERS. The LRM should be updated to allow this
case.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD