VHDL Issue Number: 1006 Classification: Language Definition Problem Language Version: VHDL-93 Summary: Parentage checks are difficult to verify during static model elaboration. Related Issues: 0176 Relevant LRM Sections: 2.2, 8.1, 8.3.1, 9.2, 11.4, 12.1 Key Words and Phrases: parent, parent checks Current Status: Closed Superseded By: N/A ----------------------- Date Submitted: 1991/03/15 Author of Submission: Paul Menchini for Daniel Barclay Author's Affiliation: Menchini & Associates Author's Post Address: 2 Davis Drive P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: 919-990-9506 Author's Fax Number: 919-990-9507 Author's Net Address: mench@mercury.interpath.net ----------------------- Date Analyzed: 1994/08/01 Author of Analysis: Daniel Barclay Revision Number: $Revision: 1.5 $ Date Last Revised: $Date: 1995/05/15 20:07:17 $ Description of Problem ---------------------- The LRM specifies six parentage checks: 1. Paragraph 7 of Section 2.2 (on page 2.5) states (in part): If a function subprogram is a parent of a given procedure, and that procedure contains a reference to a signal or variable object, then that object must be declared within the declarative region associated with the function or within the declarative region associated with the procedure. 2, 3. Paragraph 8 of Section 8.1 (on page 8-2) states: It is an error if a wait statement appears in a function subprogram, or in a procedure that has a parent that is a function subprogram. Furthermore, it is an error if a wait statement appears in an explicit process statement that includes a sensitivity list, or in a procedure that has a parent that is such a process statement. 4. Paragraph 10 of Section 8.3.1 (on page 8-5) states: If a given procedure is declared by a declarative item that is not contained within a process statement, and a signal assignment statement appears in that procedure, then the target of the assignment statement must be a formal parameter of the given procedure or of a parent of that procedure, or an aggregate of such formal parameters. 5. Paragraph 2 of Section 9.2 (on page 9-3) states (in part): Similarly, if such a process statement [i.e., one that has a sensitivity list] is a parent of a procedure, then that procedure may not contain a wait statement. 6. Paragraph 6 of Section 9.2 (on page 9-4) states (in part): A process statement is said to be a passive process if neither the process itself, nor any procedure of which the process is a parent, contains a signal assignment statement. Such checks cannot be made during analysis, since the subprogram bodies may not yet exist. Alternatively, they may exist in package bodies which, due to the order of analysis requirements (cf. Section 11.4), are not accessible during the analysis of design units making reference to items in the package interfaces corresponding to the package bodies. Moreover, such checks cannot be made during the normal execution of the model, since the checks are specified not in terms of the execution of statements, but in terms of the containment of statements. Therefore, in the general case, these checks must be made during static model elaboration. There are two requirements that make them difficult to check at this point: 1. The checks cannot be made until all packages and architectures have been elaborated. 2. For efficiency, only one instance of each process or subprogram needs to be checked--checking every instance is redundant. Because of these requirements, these checks should not be made during the normal process of elaboration. (A suitable method is a graph-coloring algorithm, similar to that used to implement the "elaborate packages required to be elaborated but not yet elaborated" requirement of Section 12.1. This algorithm can be activated once all packages and design entities have been elaborated.) Proposed Resolution ------------------- Decide when these checks should be made. Streamline them if possible. VASG-ISAC Analysis & Rationale ------------------------------ The original complainant (Daniel Barclay) retracts the original issue report. (The checks can be done before static elaboration.) VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- No change is needed. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- No change is needed.