VHDL Issue Number: 1009 Classification: Language Definition Problem Language Version: VHDL-93 Summary: Unclear context of evaluation for formal part of block map aspects. Related Issues: 0087 Relevant LRM Sections: 9.1 Key Words and Phrases: block statement, block map aspect, block formals, name evaluation context Current Status: Submitted 1076-1993 Disposition: N/A Disposition Rationale: N/A Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop (edited by Daniel Barclay) Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.8 $ Date Last Revised: $Date: 1995/05/15 21:26:37 $ Description of Problem ---------------------- (This IR superseedes IR0087). The actuals in an association element in a block generic or port map aspect are evaluated in the context of the enclosing declarative region (LRM 9.1). The obvious intent is to make block map associations parallel other forms of association in the language in that formals are not directly visible in the map aspect and instead are visible by selection at certain specific places in the map aspect. To achieve this effect, the index expressions and slice range expressions (if any) in the names of the formals should also be evaluated in the enclosing declarative region. Proposed Resolution ------------------- Evaluate such indexed name index expressions and slice name range expression in the contecxt of the enclosing declarative region. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD