VHDL Issue Number:      1012
Classification:         Language Definition Problem
Language Version:       VHDL-93
Summary:                It is unclear how Physical Literals of type TIME
                        should be treated when checking for conformance.
Related Issues:         0053, 0184 
Relevant LRM Sections:  2.7, 7.4
Key Words and Phrases:  Conformance, Static, TIME Literals
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1990/01/04
Author of Submission:   Sivaram Nayudu
Author's Affiliation:   Synopsys, Inc.
Author's Post Address:  1098 Alta Avenue
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5454
Author's Fax Number:
Author's Net Address:   nayudu@synopsys.com
-----------------------
Date Analyzed:          1994/07/25
Author of Analysis:     John Willis (willis@vnet.ibm.com)
Revision Number:        $Revision: 1.3 $
Date Last Revised:      $Date: 1995/07/26 21:48:29 $


Description of Problem
----------------------
Section 2.7, Conformance Rules, says:

    Whenever the language rules either require or allow the specification of a
    given subprogram to be provided in more than one place, the following
    variations are allowed at each place:

      o A numeric literal can be replaced by a different numeric literal if and
    only if both have the same value.

      o A simple name can be replaced by an expanded name in which ...

    Two subprogram specifications are said to conform if, apart from comments
    and the above allowed variations, both specifications are formed by the
    same sequence of lexical elements, and the corresponding lexical elements
    are given the same meaning by the visibility rules.

Let me take an example and explain the problem:

    package P1 is
    procedure PX (signal I1: in Time := 1 us; signal I2 : out Bit;
        signal I3 : inout Integer);
    end P1;

    package body P1 is
    procedure PX (signal I1: in Time := 1000 ns; signal I2 : out Bit;
        signal I3 : inout Integer) is
    begin
        assert (I1 /= 1 us)
        report "No failure on test" ;
    end PX;
    end P1;

In the example above, the initialization expression for one of the parameters
is replaced by a different expression. The question is whether the two
subprogram specifications conform?

    1.  It is obvious that two subprogram specifications are not formed by the
    same sequence of lexical elements. 

    2.  Do they have the same value?

I believe that conformance rule should be checked at analysis time.  This means
that to compare the values the two expressions must be locally static.  This
raises another difficult question.  
   
    Is a physical literal of type TIME locally static?

My view is that it is not.  Given that the timebase can be different for
different simulations, the two physical literals above will not have the same
numerical value if in one simulation a timebase of NS and another a timebase of
US is specified.

[NOTE:  This issue came up because some of the tests in VPI test suite Version
    5.0a assume that expression(s) involving time literals are locally
    static.]


Proposed Resolution
-------------------
It is necessary to exclude the numeric literal(s) of type TIME from the
variation that specifies that two subprogram specifications conform if a
numeric literal is replaced another numeric literal with same value.

Section 2.7 of the VHDL LRM should be modified to read as follows:

    Whenever the language rules either require or allow the specification of a
    given subprogram to be provided in more than one place, the following
    variations are allowed at each place:

      o A numeric literal, excluding physical literal of type TIME, can be
    replaced by a different numeric literal if and only if both have the
    same value.

      o A simple name can be replaced by an expanded name in which ...

    Two subprogram specifications are said to conform if, apart from comments
    and the above allowed variations, both specifications are formed by the
    same sequence of lexical elements, and the corresponding lexical elements
    are given the same meaning by the visibility rules.


VASG-ISAC Analysis & Rationale
------------------------------
Physical literals of type time are explicitly not locally static (see 
Section 7.4.1 of the LRM).  Thus the stated VT test is not compliant with
VHDL 1993.

The LRM does provide for the range of type Time to be implementation-defined,
and indeed many simulators do not provide for the full range of Time defined
in std.standard.

The same sort of argument could seem to be made for the comparison of 
literals having real type.

If an implementation chooses an implementation defined range for which a
given literal is not precisely representable, the literal is presumably
converted to the nearest representable literal.


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------

Literals having a value which is not precisely representable in the subtype
associated with the literal are to be rounded to the nearest representable
value.  If the literal is equal distance from two representable values, the
value closest to zero is used.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD