VHDL Issue Number:      1013
Classification:         Language Definition Problem
Language Version:       VHDL-93
Summary:                Reference to a generate loop parameter in a
                        configuration is unclear
Related Issues:         0072, 0027, 0029, 0112
Relevant LRM Sections:  9.7, 1.3
Key Words and Phrases:  Generate loop parameter, configuration declaration
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop (edited by Bill Paulsen)
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    N/A
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.6 $
Date Last Revised:      $Date: 1995/05/15 21:26:37 $


Description of Problem
----------------------
(This IR supersedes IR 0072.)

References to generate loop parameters from within a configuration are not
defined.  For example:

  architecture a of e is
  begin
    b: for i in 1 to 10 generate
      ...
       end generate;
  end a;

  configuration c of e is
    for a
      for b(i) ... end for;  -- Is b(i) legal?
    end for;
  end c;

Is the configuration valid?  If so, what does it mean?  The problem
specifically is that the point in the elaboration process at which "b(i)"
gets evaluated is not specified.


Proposed Resolution
-------------------
References to a generate loop parameter from within a configuration
should be explicitly disallowed in the LRM, in Section 1.3.1.


VASG-ISAC Analysis & Rationale
------------------------------
IR 0072, which is superseded by this IR, proposed to solve this problem by
saying that the corresponding block specifications are elaborated each
time the body of the generate statement is elaborated.  The proposal also
suggested to include the generate loop parameter in the visibility of the 
index specification of the block specification.  This solution would then
effectively make this:
  for b(i) ...
equivalent to:
  for b ...
which means for all block statements generated.  Thus, there is no additional
expressive power from this proposal.

The resolution proposed here clarifies the issue, and does not introduce
possibly confusing syntax.


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
In Section 1.3.1, add this paragraph after the third from the last paragraph
of this section, which begins "If the block specification ...":

"The index specification of a block specification does not have visibility
to the generate loop parameter of the generate statement denoted by the
generate statement label of the block specification."


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
Add the above language to the LRM.