VHDL Issue Number:      1016
Classification:         Language Definition Problem
Language Version:       VHDL-93
Summary:                LRM definition of block statements is ambiguous.
Related Issues:         0107
Relevant LRM Sections:  9 (header), 9.1
Key Words and Phrases:  Block statements, implicit declaration of labels,
                        guard expression
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1988/06/04
Author of Submission:   Paul Menchini (edited by Bill Paulsen)
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    N/A
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.7 $
Date Last Revised:      $Date: 1995/05/15 21:26:37 $


Description of Problem
----------------------
(This IR supersedes IR 0107.)

The LRM is ambiguous in several respects concerning block statements.  The
introductory part of Chapter 9, on Page 9-1, states:

        "[Concurrent statement] labels are implicitly declared at
         the beginning of the declarative part of the innermost
         enclosing ... block statement.

However, Section 9.1, on Page 9-1, says of the guard expression on a block
statement:

        "If a guard expression appears after the reserved word block,
         then a signal with the simple name GUARD if predefined type
         BOOLEAN is implicitly declared *at the beginning of the
         declarative part of the block*." [Emphasis mine.]

It is therefore unclear whether the labels or the signal GUARD appears first
when both appear in the declarative part of a block statement.

Moreover, if the block header is non-empty, it is unclear where the
declarations of the generics and ports are to appear.  By analogy with
entities, it seems that they should also appear first in the declarative region
of the block; note that this assumption exacerbates the ambiguity if labels and
the guard expression are also present.  (I have been informed by the language
developers that their intent was to include the formals in the declarative
region of the block.)


Proposed Resolution
-------------------
Define a specific order for all implicit and explicit declarations in the block
declarative region.  I would suggest that any block header "declarations"
appear first, then any labels used in the block statement part, then the
implicit signal GUARD, as appropriate.  All explicit declarations in the block
declarative part would appear last.  Of course, subject to this ordering, all
declarations appear in textual order.

To implement, I suggest that the sentence in Section 9.1 quoted above be
changed to read:

        "If a guard expression appears after the reserved word block,
         then a signal with the simple name GUARD if predefined type
         BOOLEAN is implicitly declared at the beginning of the
         declarative part of the block, unless any labeled statements
         appear immediately within the block statement part, in which
         case the implicit declaration of signal GUARD appears
         immediately after the implicit declarations of the labels."

I also suggest that one additional sentence be added to the second-to-last
paragraph (not counting the note) of Section 9.1:

        "The names of any generics or ports declared in a block header
         appear in the block's declarative region before any implicit
         or explicit declarations in the block's declarative part."


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD