VHDL Issue Number:      1031
Classification:         Language Definition Problem
Language Version:       VHDL-93
Summary:                Can targets be in the form of nested aggregates?
Related Issues:         Supersedes 0153 (Andy Tsay)
Relevant LRM Sections:  8.3, 8.4
Key Words and Phrases:  signal assignment statement, target, aggregate,
                        variable assignment statement, nested aggregate,
                        multi-dimensional aggregate
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/12
Author of Submission:   Paul Menchini
Author's Affiliation:   Menchini & Associates
Author's Post Address:  2 Davis Drive
                        P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  919.990.9506
Author's Fax Number:    919.990.9507
Author's Net Address:   mench@mercury.interpath.net
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.4 $
Date Last Revised:      $Date: 1995/04/14 00:13:44 $


Description of Problem
----------------------
Can the target of a signal assignment statement or a variable assignment
statement be a nested aggregate?  I.e., is the following VHDL fragment legal?

            :
        type A is array (1 to 2, 1 to 2) of Bit;
        signal S: A;
        signal B1, B2, B3, B4: Bit;
            :
        ((B1, B2), (B3, B4)) <= S;
            :

The LRM appears to declare this example to be illegal.  Consider paragraph 3 of
Section 8.3 (on page 8-3):

        If the target of the signal assignment statement is in the form
        of an aggregate, then ... the expression in each element
        association of the aggregate must be a locally static name that
        denotes a signal.

Unfortunately, the actuals in the element associations of (the top-level of)
this example target are not locally static signal names, but are in the form of
subaggregates.

There appears to be no need for this one-dimensional restriction; it merely
appears to be a case where the LRM uses iterative language to explain a
recursive concept.


Proposed Resolution
-------------------
Allow targets in the form of nested aggregates.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD