VHDL Issue Number:      1077
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-93
Summary:                Out ports cannot drive buffer ports.
Related Issues:         None.
Relevant LRM Sections:  1.1.1.2
Key Words and Phrases:  buffer, mode, association
Current Status:         Submitted     
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1994/03/23 
Author of Submission:   Paul Menchini
Author's Affiliation:   Menchini & Associates
Author's Post Address:  2 Davis Drive
                        P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  919-990-9506
Author's Fax Number:    919-990-9507
Author's Net Address:   mench@mench.com
-----------------------
Date Analyzed:          TBD 
Author of Analysis:     TBD 
Revision Number:        $Revision: 1.2 $
Date Last Revised:      $Date: 1995/05/25 18:39:14 $


Description of Problem
----------------------
When building structural descriptions, it is often desirable to declare
the port of a design entity to be of mode buffer, as the value of the port
is to be generated and used in the structural description.

As an example, consider the following D-Latch, described using NAND gates:

    entity  DLatch  is
        port (D, Ena:   in      Bit;
              Q, QBar:  buffer  Bit);
    end entity DLatch;

    architecture Structure of DLatch is
        component NAND2 is
            port (X, Y: in  Bit;
                  O:    out Bit);
        end component NAND2;

        signal DBar, Set, Reset:  Bit;
    begin
        Q1: NAND2   port map (D,     D,    DBar);
        Q2: NAND2   port map (D,     Ena,  Set);
        Q3: NAND2   port map (DBar,  Ena,  Reset);
        Q4: NAND2   port map (Set,   QBar, Q);      -- illegal!
        Q5: NAND2   port map (Reset, Q,    QBar);   -- illegal!
    end architecture Structure;

As natural as this example is, it is illegal VHDL.  There are two instances
of actual ports of mode buffer associated with formal ports of mode out
([O =>] Q in instance Q4 and [O =>] QBar in instance Q5).

By P1076-1992/C+, Section 1.1.1.2, lines 110-111 (page 7), these associations
are illegal, as 

    2.  For a formal of mode OUT,
                 the associated actual may only be a port of mode OUT or
                 INOUT.

Note that a dataflow architecture, otherwise identically constructed, is legal:

    architecture Dataflow of DLatch is
        signal DBar, Set, Reset:  Bit;
    begin
        Q1: DBar   <=  D     nand D;
        Q2: Set    <=  D     nand Ena;
        Q3: Reset  <=  DBar  nand Ena;
        Q4: Q      <=  Set   nand QBar;
        Q5: QBar   <=  Reset nand Q;
    end architecture Dataflow;

Apparently, the restrictions on buffer ports are intended to ensure that the
driving and effective values of a buffer port are the same.  To this end,

    For a formal of mode BUFFER, the associated actual may only be
    a port of mode BUFFER.

(P1076-1992/C+, Section 1.1.1.2, lines 114-115 ,page 7), and

    A buffer port may have at most one source....  Furthermore, ...
    any actual associated with a formal buffer port may have at most
    one source.

(P1076-1992/C+, Section 1.1,1,2, lines 118-120, page 8).

The restriction on lines 114-115 seems to imply that not only are the effective
and driving values of a given buffer port the same, but that all ports and
signals participating in the buffer port's network have the same effective and
driving value.

However, buffer ports appearing as formals in port maps may be type converted
(P1076-1992/C+, Section 3.2.1.1, lines 460-461, page 44).  Thus, there are
networks containing buffer ports where the effective and driving values are
not everywhere the same.

Thus, it seems that the restrictions of lines 110-111 of Section 1.1.1.2 may
be relaxed without disturbing the desirable property that the effective and
driving values of a given buffer port be the same.


Proposed Resolution
-------------------
Modify Section 1.1.1.2, lines 110-111 (page 7), to read:

    2.  For a formal of mode OUT,
                 the associated actual may only be a port of mode OUT, INOUT,
                 or BUFFER.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD