VHDL Issue Number: 1090 Classification: Language Definition Problem Language Version: VHDL-93 Summary: Do library clauses extend from entities to architectures? Related Issues: 1050 Relevant LRM Sections: 10.1, 11.2, 11.3 Key Words and Phrases: Declarative Regions, Design Libraries, Context Clauses Current Status: Submitted 1076-1993 Disposition: N/A Disposition Rationale: N/A Superseded By: N/A ----------------------- Date Submitted: 1994/07/25 Author of Submission: Charles Swart Author's Affiliation: Mentor Graphics Corporation Author's Post Address: 8005 S.W. Boeckman Road Wilsonville, OR 97070-7777 Author's Phone Number: (503) 685-1332 Author's Fax Number: (503) 685-1268 Author's Net Address: chuck_swart@mentorg.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.4 $ Date Last Revised: $Date: 1995/05/15 20:07:17 $ Description of Problem ---------------------- Is the following VHDL code legal? library ieee; entity e; end e; use ieee.std_logic_1164.all; architecture a of e is begin end a; Some implementations reject "use ieee...", claiming that the name ieee is not visible. Other implementations accept the use clause, claiming that since the architecture and entity together form a single declarative region, this is legal code. These differences among implementations causes serious portability problems. Proposed Resolution ------------------- This is illegal VHDL. The LRM states that an entity declaration, together with a corresponding architecture body, form a single declarative region. However, neither the library clause nor the use clause occur within this single declarative region. The reference to ieee in the use clause violates the "declare before reference" principle of VHDL. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD