VHDL Issue Number:      1097
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-93
Summary:                Why do primary unit names in secondary units differ?
Related Issues:         
Relevant LRM Sections:  1.2, 1.3, 2.6
Key Words and Phrases:  secondary units, primary unit names, simple names
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1994/09/08
Author of Submission:   Daniel S. Barclay
Author's Affiliation:   COMPASS Design Automation, Inc.
Author's Post Address:  5457 Twin Knolls Rd.
                        Suite 100
                        Columbia, MD  21045  USA
Author's Phone Number:  410-992-5700
Author's Fax Number:    410-992-3536
Author's Net Address:   daniel@compass-da.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.8 $
Date Last Revised:      $Date: 1995/05/15 20:07:17 $


Description of Problem
----------------------
In architecture bodies and configuration declarations, the name of the
entity is a general name; but in package bodies, the name of the package
is a simple name.

Is there a reason for this difference?

Proposed Resolution
-------------------
Remove the difference if there's no need for it.  Probably, these all should 
have been simple names, though for upward compatibility maybe they should be
general names.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD