VHDL Issue Number: 1119 Classification: Language Definition Problem Language Version: VHDL-93 Summary: LRM is not clear as to when the wait statement condition clause is evaluated in a postponed process. Related Issues: Relevant LRM Sections: 8.1 line 73, 9.2 line 122, 12.6.4 line 650 to 653 and line 660 Key Words and Phrases: wait statement, postponed process, resume, execute Current Status: Submitted 1076-1993 Disposition: N/A Disposition Rationale: N/A Superseded By: N/A ----------------------- Date Submitted: 1995/08/09 Author of Submission: Steven Greenberg Author's Affiliation: Analogy, Inc. Author's Post Address: 9205 SW Gemini Drive Beaverton, OR 97008 Author's Phone Number: (503) 520-2717 Author's Fax Number: (503) 643-3361 Author's Net Address: steveg@analogy.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.1 $ Date Last Revised: $Date: 1995/08/09 21:14:53 $ Description of Problem ---------------------- Section 8.1 of the LRM says that a process resumes as a result of an event on any signal in the sensitivity set of the wait statement. "If such an event occurs, the condition of the condition clause is evaluated. If the value of the condition is TRUE, the process will resume. If the value of the condition is FALSE, the process will resuspend." In the notes for section 9.2, the LRM states, "The conditions that cause a process to resume execution may no longer hold at the time the process resumes execution if the process is a postponed process." The simulation cycle described in section 12.6.4 differentiates between a process resuming (see step d) and a process executing (see step e and g). A postponed process resumes in step d, but executes in step g. Clearly in step d, any process that is sensitive to a signal on which an event has occurred resumes. Will the process execute in step g if there is no longer an event on any signal for which the wait statement is sensitive by the time the simulation cycle gets to step g? Is the condition tested in step d or is it tested in step g? Unlike section 12.6.4, section 9.2 uses the words resume and execution together so it is no help in separating out step d and step g. Section 8.1 uses only the word resume. If this means that the evaluations should occur in step d, then what is the significance of the note in section 9.2? Does it mean that the model writer must put statements in the process to re-evaluate the wait statement condition to make sure that it is really ok to execute? If you want to use a postponed process to only look at signals that change in a simulation time slot, then evaluating the wait statement sensitivity in step d may cause execution of a process for a signal that returned to its original value before the process gets to execute. However, evaluating it in step g may cause you to fail to examine a signal that changed value in an earlier delta cycle, but that was quiet in the delta cycle of which step g is a part. The model writer can write HDL code to ameliorate problems from evaluation in step d, but cannot do so for problems caused by evaluation in step g. Proposed Resolution ------------------- Make it clear that the sensitivity list and the condition are evaluated in step d for a postponed process (if that is what is intended). Make the use of the words resume and execute in sections 8.1, 9.2, and 12.6.4 consistent. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD