Enclosed are
1. The minutes--Review for action items.
NOTE: please let me know if the next scheduled meeting day/time is OK
2. Active IR list.
3. IR 2004.
Please vote on this IR. The proposal is that it be ISAC approved.
No one seems too excited about the proposed solution ("no change")
but it seems to be the most practical. If you have other suggestions,
let me know, and we'll reopen the discussion.
I should mention that I tried to look up shift instructions for several
architectures. Many do not have SLA instructions.
Intel and AMD 32 bit architectures state that SLA is identical to SLL
One local expert claims that a SLA should overflow if and of the shifted
left bits
change value from the final left bit.
Chuck Swart
Minutes of ISAC meeting held via telecom on
23 November 2004.
Present: Peter Ashenden, Jim Lewis, Larry Soule, Chuck Swart
Absent: Deepak Pant, Ajay Varikat
Next Meeting: Thursday 09 December 2004 7pm Pacific Time.
Note: Please let me (Chuck) know if this day is OK.
TOPIC: IR2047 Backslash in extended identifiers
Peter's analysis is accepted. ISAC-Approved
ACTION: Chuck to forward to VASG chair.
TOPIC: IR2000 Where may/must deferred constant declaration appear
Ajay's suggestion to add the word "anywhere" to the suggested wording
was accepted. ISAC-Approved.
ACTION: Chuck to forward to VASG chair.
TOPIC: IR2008 Source value of undriven, non-sourced INOUT, OUT or BUFFER port
It was agreed that appropriate comments should be added to both
sections 4.3.2 and 12.6.2.
ACTION: Peter to update (done)
Chuck: submit for electronic vote.
ALL: Vote electronically on this issue.
TOPIC: IR2040 Problems with OTHERS in aggregates
Ajay's analysis was discussed. An outside reviewer commented that
and aggregate doesn't have an "index subtype" but, instead, and
"index range." This misnaming occurs in many places in the LRM, particularly
in section 7.3.2.2. Other sections which should be examined include
3.2.1 array types
3.2.1.1 index constraints
ACTION: Chuck to update IR to reflect this. Chuck to consult with
Ajay on this.
TOPIC: IR2004 Definition of SLA doesn't make sense
The example which was submitted will be clearer if
1 sla 1 == 3
is replaced by bit vector equivalents.
There was discussion about how other representations were overloading
SLA. The general consensus (Chuck believes) is that the current LRM
wording is as good as any, so backward compatibility issues dictate that
no changes be made.
ACTION: Chuck to update IR and to submit for electronic vote.
ALL: vote on this IR.
TOPIC: IR2009 New std package, containing compiler and target identification information
This topic need to be addressed by the VHDL200x environment group.
ACTION: Chuck to forward to VASG chair.
TOPIC: IR2010 The description of type/subtype relationship could be better
Peter's analysis was accepted.
ACTION: Chuck to submit for electronic vote.
ALL: Vote on this IR.
TOPIC: IR2011 A package body should be able to consist of several files
The submitter's issue is unclear, but the request itself should be forwarded
to the Modeling and Productivity group.
ACTION: Chuck to submit for electronic vote.
ALL: Vote on this IR.
TOPIC: IR2012 VHDL lacks inherent statements to describe the most basic hardware design equations
This request should be forwarded to the Modeling and Productivity group.
ACTION: Chuck to submit for electronic vote.
ALL: Vote on this IR.
TOPIC: IR2013 Exact subtype "matching" for port associations
This IR touches on a very difficult issue--that of signals as subprogram
parameters. Chuck will collect information relevant to this topic.
ACTION: Chuck to gather "pre-analysis" information.
TOPIC: IR2014 Allowance of the keyword "all" in place of a sensitivity list is desirable
This is FT-19.
ACTION: Chuck to submit for electronic vote.
ALL: Vote on this IR.
Active IRs:
No Status Responsible Description Notes
Summary
2004 Analyzed Chuck Definition of SLA doesn't make sense
2008 Analyzed Peter Source value of undriven, non-sourced INOUT, OUT or BUFFER port
2010 Analyzed Peter The description of type/subtype relationship could be better
2011 Analyzed Peter A package body should be able to consist of several files
2012 Analyzed Peter VHDL lacks inherent statements to describe the most basic hardware design equations
2013 Submitted Exact subtype "matching" for port associations
2014 Analyzed Peter Allowance of the keyword "all" in place of a sensitivity list is desirable
2015 Analyzed Peter Generics should be able to incorporate other generics
2018 Analyzed Peter Variable IN parameter should be no different than constant
2019 Analyzed Peter Reading outputs from within architecture
2020 Analyzed Peter keyword REPORT is over-used
2021 Analyzed Peter Dynamic hardware construct
2022 Submitted Elements of constant composite to be locally static
2023 Analyzed Peter Add predefined array types for integer, boolean, real and time
2024 Analyzed Peter VHDL needs encryption support
2025 Analyzed Peter "Generate" for sequential code
2026 Analyzed Peter Upward propagating parameters
2028 Analyzed Peter Clarify simulation cycle.
2038 Submitted Minor semantic errors
2040 Analyzed Ajay Problems with OTHERS in aggregates
2041 Analyzed Chuck Association of members is too restricted
2042 Analyzed Peter Architecture as a block causes problems
2043 Submitted Deepak? Numeric VALUE attribute parameter can't have sign
2044 Analyzed Chuck Deprecation of linkage ports affects boundary scan description language
Recent Inactive IRs
1044 ISAC-Approved Definition of 'HIGH and 'LOW in a null range
2000 ISAC-Approved Where may/must deferred constant declaration appear
2001 ISAC-Approved Resize not working in numeric_std.vhd (1076.3
2002 ISAC-Approved Resize(R.2) function in numeric_std.vhd does improper array length check
2003 Forwarded Specification of multi-cycle paths
2005 Duplicate sla operator behavior does not match typical hardware behavior
2006 Forwarded "else" in "if generate"?
2007 Forwarded VHDL needs to be enhanced to allow the modeling of switches.
2009 Forwarded New std package, containing compiler and target identification information
2016 Duplicate Allowance of the keyword "all" in place of a sensitivity list is desirable
2017 Duplicate Generics should be able to incorporate other generics
2027 Forwarded When loop index is static, drivers are created for each element of array
2029 ISAC-Approved Non-relevant words and paragraph.
2030 ISAC-Approved What signature does a method have
2031 ISAC-Approved "mod" function needed for TIME
2032 ISAC-Approved Function "now" is not pure
2033 Forwarded Incremental operator and auto subtype boundary wrap
2034 Forwarded Introduce history attribute on signals to auto infer registers
2035 Forwarded new function "stages" automates pipelining
2036 ISAC-Approved protected_type_declarative_item includes subprogram_specification
2037 ISAC-Approved Typo wrt now in the index
2039 ISAC-Approved Minor typos
2045 ISAC-Approved Add the ability to comment an entire block of code
2046 Forwarded Type independent ports and subprogram parameters
2047 ISAC-Approved Backslash in extended identifiers
VHDL Issue Number: 2004
Language_Version: VHDL-2002
Classification: Language Definition Problem
Summary: Definition of SLA doesn't make sense
Relevant_LRM_Sections: 7.2.3
Related_Issues:
Key_Words_and_Phrases: SLA
Authors_Name: Paul Graham
Authors_Phone_Number:
Authors_Fax_Number:
Authors_Email_Address: pgraham@cadence.com
Authors_Affiliation:
Authors_Address1:
Authors_Address2:
Authors_Address3:
Current Status: Submitted
Superseded By:
------------------------
Date Submitted: 04 August 2000
Date Analyzed: 28 October 2004
Author of Analysis: Chuck Swart
Revision Number: 2
Date Last Revised: 05 November 2004
Description of Problem
----------------------
The definition of sla in the 1993 LRM is kind of weird. It basically
preserves the parity bit of the left input, so that, for bit vectors:
"001" sla 1 evaluates to "011"
which might be interpreted as
1 sla 1 == 3
etc. I have never seen a computer opcode which implements this
function, though sll, srl, and sra opcodes are ubiquitous. ?
Proposed Resolution
-------------------
Why not just define sla to be the same as sll (as in Verilog)
VASG-ISAC Analysis & Rationale
------------------------------
The SLA operator was added to provide a symmetric set of left and
right shift operators. As currently defined, these operators make no
assumptions about whether the left bit of a bit vector or the right
bit is signed. Notice that these operators are only defined for
vectors of type bit or of type boolean. The intent is that all shift
operators can be overloaded to achieve any desired semantic
interpretation.
VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
No change is needed for the current version.
VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
No change is needed for future versions. However, there are currently
attempts to extend the shift operators to a larger class of types. If
these extended definitions treat the predefined SLA operator for these
types in a different way than the existing LRM states, then there will
be a conflict between the need for uniform semantics for the
predefined operators and the requirement for backward compatibility.
Received on Wed Dec 1 14:47:39 2004
This archive was generated by hypermail 2.1.8 : Wed Dec 01 2004 - 14:47:40 PST