Please review this IR for our upcoming meeting. Chuck -------------BEGINNING OF IR---------------- VHDL Issue Number: 2069 Language_Version VHDL-2002 Classification Language Definition Problem Summary Visibility of generics in block configurations Relevant_LRM_Sections Sec 1.3.1, 10.2, 10.3 Related_Issues Key_Words_and_Phrases Authors_Name Nitin Khurana Authors_Phone_Number +91-120-2562842 extn 4142 Authors_Fax_Number Authors_Email_Address nkhurana@cadence.com Authors_Affiliation Cadence Design Systems Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Analyzed Superseded By: ------------------------ Date Submitted: 19 July 2005 Date Analyzed: 09 August 2005 Author of Analysis: Chuck Swart Revision Number: 1 Date Last Revised: 09 August 2005 Description of Problem ---------------------- Please see the following VHDL descriptions. entity bug3 is generic ( Dwidth3 : integer :: 0 ); end bug3; architecture rtl_bug3 of bug3 is begin end rtl_bug3; entity bug2 is end bug2; architecture rtl_bug2 of bug2 is component virtual_bug3 generic ( Dwidth3 : integer := 0 ); end component; begin U1 : virtual_bug3; end rtl_bug2; entity bug is generic ( Dwidth : integer ); end bug; architecture rtl_bug of bug is component virtual_bug2 end component; begin U1 : virtual_bug2; end rtl_bug; configuration bug_cfg of bug is for rtl_bug for U1 : virtual_bug2 use entity work.bug2(rtl_bug2); for rtl_bug2 for U1: virtual_bug3 use entity work.bug3(rtl_bug3) generic map( DWidth3 => DWidth -- Problem ); end for; end for; end for; end for; end bug_cfg; The line in the configuration with the comment "--problem" maps a generic of component bug3 to a generic of entity bug. This mapping skips the intermediate entity bug2. Is this legal VHDL? Different tools appear to interpret this differently. According to my interpretation of section 1.3.1 of the LRM, the generics of entity bug are not visible at this point, and hence it is illegal. However, others quote section 10.2 and 10.3 to claim that it is legal. Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ We are examining the visibility of DWidth, which is used in a component configuration which lies within the component configuration of U1. The component configuration which reads For U1: virtual_bug2 use entity work.bug2(rtl_bug2)); configures an external block. Therefore visibility affecting blocks configured within this block is determined by rules which apply to external blocks. The most applicable paragraph is in clause 1.3.1 Block Configuration: "If the scope of a declaration (see 10.2) includes the end of the declarative part of a block corresponding to a given block configuration,then the scope of that declaration extends to each configuration item contained in that block configuration,with the exception of block configurations that configure external blocks. Similarly, if a declaration is visible (either directly or by selection) at the end of the declarative part of a block corresponding to a given block configuration,then the declaration is visible in each configuration item contained in that block configuration,with the exception of block configurations that configure external blocks." This rule states that visibility of declarations does not extend into external blocks. In addition, we have the following LRM statements: Clause 10.2 Scope of declarations: "In addition to the above rules,the scope of any declaration that includes the end of the declarative part of a given block (whether it be an external block defined by a design entity or an internal block defined by a block statement)extends into a configuration declaration that configures the given block." This deals with the mirror issue. Declarations that are visible within the design entity which configures the external block are still visible. "If a component configuration appears as a configuration item immediately within a block configuration that configures a given block,and if the scope of a given declaration includes the end of the declarative part of that block,then the scope of the given declaration extends from the beginning to the end of the declarative region associated with the given component configuration.A similar rule applies to a block configuration that appears as a configuration item immediately within another block configuration,provided that the contained block configuration configures an internal block. Furthermore,the scope of a use clause is similarly extended. Finally,the scope of a library unit contained within a design library is extended along with the scope of the logical library name corresponding to that design library." This rule extends scope of items declared in configurations into internal blocks, but does not extend this scope into external blocks. Clause 10.3 Visibility "In addition to the aforementioned rules,any declaration that is visible by selection at the end of the declarative part of a given (external or internal) block is visible by selection in a configuration declaration that configures the given block." This rule extends visibility by selection from design entities into the external block which they configure. "If a component configuration appears as a configuration item immediately within a block configuration that configures a given block,and if a given declaration is visible by selection at the end of the declarative part of that block,then the given declaration is visible by selection from the beginning to the end of the declarative region associated with the given component configuration.A similar rule applies to a block configuration that appears as a configuration item immediately within another block configuration,provided that the contained block configuration configures an internal block." This rule extends visibility by selection from configurations to internal blocks, but does not extend this visibility into external blocks. "If a component configuration appears as a configuration item immediately within a block configuration that configures a given block,and if a given declaration is directly visible at the end of the declarative part of that block,then the given declaration is visible by selection from the beginning to the end of the declarative region associated with the given component configuration.A similar rule applies to a block configuration that appears as a configuration item immediately within another block configuration,provided that the contained block configuration configures an internal block." This rule extends visibility of a item declared in a block into the immediate component configuration and to nested configurations associated with internal blocks. The LRM is consistent: The intent is to pass information into external blocks only through its ports and generics. The conclusion of the ISAC is that the provided example is illegal. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change to the LRM. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- No change to the LRM. -------------END OF IR---------------- Revised 09 August 2005 No Status Responsible Description Notes Active IRs 2038 Submitted Minor semantic errors 2054 Submitted Larry Individ. assoc. rules for array formal are not valid 2065 Analyzed Chuck OTHERS in aggregates too restrictive 2069 Analyzed Chuck Visibility of generics in block configurations 2070 Submitted Support for floating point denormal numbers Resolved IRs 1044 VASG-Approved Definition of 'HIGH and 'LOW in a null range 2000 VASG-Approved Where may/must deferred constant declaration appear 2001 VASG-Approved Resize not working in numeric_std.vhd (1076.3 2002 VASG-Approved Resize(R.2) function in numeric_std.vhd does improper array length check 2003 Forwarded Specification of multi-cycle paths 2004 VASG-Approved Definition of SLA doesn't make sense 2005 Duplicate sla operator behavior does not match typical hardware behavior 2006 Forwarded "else" in "if generate"? 2007 Forwarded VHDL needs to be enhanced to allow the modeling of switches. 2008 VASG-Approved Source value of undriven, non-sourced INOUT, OUT or BUFFER port 2009 Forwarded New std package, containing compiler and target identification information 2010 VASG-Approved The description of type/subtype relationship could be better 2011 Forwarded A package body should be able to consist of several files 2012 Forwarded VHDL lacks inherent statements to describe the most basic hardware design equations 2013 VASG-Approved Exact subtype "matching" for port associations 2014 Forwarded Allowance of the keyword "all" in place of a sensitivity list is desirable 2015 Forwarded Generics should be able to incorporate other generics 2016 Duplicate Allowance of the keyword "all" in place of a sensitivity list is desirable 2017 Duplicate Generics should be able to incorporate other generics 2018 VASG-Approved Variable IN parameter should be no different than constant 2019 Forwarded Reading outputs from within architecture 2020 ISAC-Approved Keyword REPORT is over-used 2021 Forwarded Dynamic hardware construct 2022 Forwarded Elements of constant composite to be locally static 2023 VASG-Approved Add predefined array types for integer, boolean, real and time 2024 Forwarded VHDL needs encryption support 2025 Forwarded "Generate" for sequential code 2026 Forwarded Upward propagating parameters 2027 Forwarded When loop index is static, drivers are created for each element of array 2028 ISAC-Approved Clarify simulation cycle. 2029 ISAC-Approved Non-relevant words and paragraph. 2030 VASG-Approved What signature does a method have 2031 ISAC-Approved "mod" function needed for TIME 2032 VASG-Approved Function "now" is not pure 2033 Forwarded Incremental operator and auto subtype boundary wrap 2034 Forwarded Introduce history attribute on signals to auto infer registers 2035 Forwarded new function "stages" automates pipelining 2036 VASG-Approved protected_type_declarative_item includes subprogram_specification 2037 VASG-Approved Typo wrt now in the index 2039 VASG-Approved Minor typos 2040 VASG-Approved Problems with OTHERS in aggregates 2041 Forwarded Association of members is too restricted 2042 VASG-Approved Architecture as a block causes problems 2043 ISAC-Approved Numeric VALUE attribute parameter can't have sign 2044 VASG-Approved Deprecation of linkage ports affects boundary scan description language 2045 VASG-Approved Add the ability to comment an entire block of code 2046 Forwarded Type independent ports and subprogram parameters 2047 VASG-Approved Backslash in extended identifiers 2048 VASG-Approved Miscellaneous errors 2049 VASG-Approved Circular definition of an event on a signal 2050 ISAC-Approved Definition of S'Last_Value was apparently broken in 1993 2051 VASG-Approved Path_name and instance_name do not allow for protected types 2052 VASG-Approved Path_name and instance_name don't deal with operator symbols 2053 ISAC-Approved Minor Typos in VHDL 2002 part 2 2055 VASG-Approved Prohibition on assignment of protected types not normative 2056 VASG-Approved Can an attribute name that denotes a function be used where a name is required? 2057 VASG-Approved Access-typed parameters to predefined "=" and "/=" 2058 VASG-Approved Does USE of type name make operators and literals visible? 2059 ISAC-Approved Upper/lower case character mapping is not clear 2060 Forwarded Include truth table for multi-input/multi-output logic. 2061 ISAC-Approved Default actions on severity flags is different between simulators 2062 ISAC-Approved Range staticness 2064 ISAC-Approved Type conversion of unconstrained output in a port map 2063 Forwarded Unconstrained array formals should not get subtype from actuals 2066 Forwarded Multidimensional array in IEEE Std 1076.6-2004 2067 Forwarded Enhancement: Logical link interface abstraction 2068 ISAC-Approved Entity instantiation with space before the entity nameReceived on Tue Aug 9 14:47:06 2005
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