Note that there is an analysis which proposes two possible solutions, but it doesn't make a recommendation (yet). Don't forget to prepare for the meeting in one week! Chuck Swart h-------------BEGINNING OF IR---------------- VHDL Issue Number: 2085 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary What happens when a parameter of mode out is not assigned in a procedure? Relevant_LRM_Sections 2.1.1.1 Related_Issues Key_Words_and_Phrases procedures, out Authors_Name Larry Soule Authors_Phone_Number 650-584-1919 Authors_Fax_Number Authors_Email_Address larrys@synopsys.com Authors_Affiliation Synopsys Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Analyzed Superseded By: ------------------------ Date Submitted: 8 February 2006 Date Analyzed: 09 March 2006 Author of Analysis: Chuck Swart Revision Number: 1 Date Last Revised: 09 March 2006 Description of Problem ---------------------- Here is an example of a procedure with an out-mode parameter that is conditionally assigned. architecture a of e is subtype t is bit_vector(1 to 4); constant c : t := (others => '1'); procedure p(i : in integer; o : out t) is begin if i > 0 then o := c; end if; end procedure; Section 2.1.1.1 says that only for in and inout parameters is the value copied in (when using pass by copy). When exiting the procedure, inout and out parameters are copied back in. If the out mode formal is not assigned in the procedure, this has the effect of writing t'left back into the actual which seem counter-intuitive. At least 2 VHDL implementations known to me handle this differently. Proposed Resolution ------------------- Specify that only parameters of mode out that have been assigned inside the procedure get copied out. VASG-ISAC Analysis & Rationale ------------------------------ One way to view this problem is to ask the question: Do out mode parameters get initialized (presumably to the appropriate 'left value)? Because of the copy-in semantics for objects of mode in or mode inout, this question is moot for other modes. Also, The rules for signal parameters make this question meaningless for signals. That leaves the question for out mode variables. The LRM is not completely clear on this issue. Section 12.5 states: "Execution of a subprogram call involves the elaboration of the parameter interface list of the corresponding subprogram declaration; this involves the elaboration of each interface declaration to create the corresponding formal parameters." Elaboration of interface declarations is not defined explicitly. However, section 12.3.1.4 Deals with Object declarations: "Elaboration of an object declaration that declares an object other than a file object or an object of a protected type proceeds as follows: ... b) If the object declaration includes an explicit initialization expression, the the initial value of the object is obtained by evaluating the expression....Otherwise, any implicit initial value for the object is determined. c) the object is created. d) Any initial value is assigned to the object." Its not clear whether or not this clause refers to interface declarations. Clause 4.3.1 Object declarations, states: object_declaration ::= constant_declaration |signal_declaration |variable_declaration |file_declaration These are syntactic constructs which are not interface declarations. This seems to imply that object declarations are not intended to include interface declarations. Also, in the above clause, the meaning of section b) is unclear. Out mode parameters must not contain an explicit initialization expression (such expressions are interpreted as the value for the parameter if left unassociated.) So its not clear whether or not an implicit initial value for the object applies. There are (at least) two possible solutions to the problem. 1. Extend copy-in semantics to include out mode parameters. This has the advantage that values which are not updated within the subprogram are unchanged. This solution also works well with pass by reference implementations. (There might be a problem with access types?) 2. Change clause 12.3.1.4 to specifically refer to interface declarations (or add a new clause). This solution seems to meet the VHDL principle that all variables are initialized, and the initialization of interface declaration would be virtually the same as that for local variables in the subprogram. There is a potential performance problem, in that arrays which are passed by reference would have to be initialized each time a subprogram was called. Its not clear whether either of these solutions would affect backward compatibility. It does seem that different implementations have treated this problem in different ways, so some sort of backward incompatibility may be inevitable. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------Received on Thu Mar 9 16:29:43 2006
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