Both enclosures are also available online. Chuck Swart -------------BEGINNING OF IR---------------- VHDL Issue Number: 2083 Language_Version VHDL-2002 Classification Language Definition Problem Summary Generate index specification should be of same subtype as generate parameter Relevant_LRM_Sections 1.3.1 Block configuration 9.7 Generate statements 12.4.2 Generate statements Related_Issues Key_Words_and_Phrases generate parameter, block configuration, index specification Authors_Name Peter Ashenden Authors_Phone_Number +61 414 709 106 Authors_Fax_Number Authors_Email_Address peter@ashenden.com.au Authors_Affiliation Ashenden Designs Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Analyzed Superseded By: ------------------------ Date Submitted: 31 January 2006 Date Analyzed: 15 March 2006 Author of Analysis: Chuck Swart Revision Number: 1 Date Last Revised: 15 march 2006 Description of Problem ---------------------- I've just been looking at generate statements, and am having trouble finding rules that I thought should exist. A for-generate statement specifies values for the generate parameter with a discrete range. The implicit type of the generate parameter is the base type of the discrete range. In a block configuration for the generate statement, you can write a block specification that determines which occurrences of the generate get configured. The block specification can be either a discrete range or an expression. I would expect the type of the discrete range or expression to be that of the generate parameter, and that values in the discrete range or the value of the expression be in the discrete range of the generate statement. However, I can't find rules that state this. Proposed Resolution ------------------- If no such rule exists anywhere, add a rule to 1.3.1 specifying that the value or values of the index specification be of the type of the corresponding generate parameter and lie within the discrete range specified for the generate parameter. VASG-ISAC Analysis & Rationale ------------------------------ The submitter is correct. The rules he describes do not exist in the LRM. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- Interpret the LRM as if the Recommendation for Future Revisions had been adopted. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- In clause 1.3.1 there is a paragraph which reads: "If the block specification of a block configuration contains a generate statement label, and if this label contains an index specification, the it is an error if the generate statement denoted by the label does not have a generation scheme including the reserved word for." Add to the end of this paragraph: "In addition, the value (or values) of the index specification must be of the type of the corresponding generate parameter and this value (or these values) must lie within the discrete range specified for the generate parameter." -------------END OF IR---------------- Revised 15 March 2006 Number Status Responsible Description Notes Active IRs 2038 Submitted Ajay Minor semantic errors 2054 Analyzed Larry Individual assoc. rules for array formal are not valid 2062 (Analyzed) Chuck Range staticness 2074 Analyzed Chuck & Ajay Problem with direct/select visibility in formal part 2077 Analyzed Larry Incorrect wording on some language constructs 2079 Analyzed Chuck Is TIME a locally static type? 2082 Submitted Chuck Elaboration of unconstrained interface objects 2083 Analyzed Chuck Generate index specification should be of same subtype as generate parameter 2084 Analyzed Peter A record "element" is not called a "field" 2085 Analyzed Chuck What happens when a parameter of mode out is not assigned in a procedure? 2086 Analyzed Chuck Incorrect description of type mark in disconnection specification 2087 Analyzed Larry Ambiguous rule for type of an alias declaration Resolved IRs 1044 VASG-Approved Definition of 'HIGH and 'LOW in a null range 2000 VASG-Approved Where may/must deferred constant declaration appear 2001 VASG-Approved Resize not working in numeric_std.vhd (1076.3 2002 VASG-Approved Resize(R.2) function in numeric_std.vhd does improper array length check 2003 Forwarded Specification of multi-cycle paths 2004 VASG-Approved Definition of SLA doesn't make sense 2005 Duplicate sla operator behavior does not match typical hardware behavior 2006 Forwarded "else" in "if generate"? 2007 Forwarded VHDL needs to be enhanced to allow the modeling of switches. 2008 VASG-Approved Source value of undriven, non-sourced INOUT, OUT or BUFFER port 2009 Forwarded New std package, containing compiler and target identification information 2010 VASG-Approved The description of type/subtype relationship could be better 2011 Forwarded A package body should be able to consist of several files 2012 Forwarded VHDL lacks inherent statements to describe the most basic hardware design equations 2013 VASG-Approved Exact subtype "matching" for port associations 2014 Forwarded Allowance of the keyword "all" in place of a sensitivity list is desirable 2015 Forwarded Generics should be able to incorporate other generics 2016 Duplicate Allowance of the keyword "all" in place of a sensitivity list is desirable 2017 Duplicate Generics should be able to incorporate other generics 2018 VASG-Approved Variable IN parameter should be no different than constant 2019 Forwarded Reading outputs from within architecture 2020 VASG-Approved Keyword REPORT is over-used 2021 Forwarded Dynamic hardware construct 2022 Forwarded Elements of constant composite to be locally static 2023 VASG-Approved Add predefined array types for integer, boolean, real and time 2024 Forwarded VHDL needs encryption support 2025 Forwarded "Generate" for sequential code 2026 Forwarded Upward propagating parameters 2027 Forwarded When loop index is static, drivers are created for each element of array 2028 VASG-Approved Clarify simulation cycle. 2029 VASG-Approved Non-relevant words and paragraph. 2030 VASG-Approved What signature does a method have 2031 VASG-Approved "mod" function needed for TIME 2032 VASG-Approved Function "now" is not pure 2033 Forwarded Incremental operator and auto subtype boundary wrap 2034 Forwarded Introduce history attribute on signals to auto infer registers 2035 Forwarded new function "stages" automates pipelining 2036 VASG-Approved protected_type_declarative_item includes subprogram_specification 2037 VASG-Approved Typo wrt now in the index 2039 VASG-Approved Minor typos 2040 VASG-Approved Problems with OTHERS in aggregates 2041 Forwarded Association of members is too restricted 2042 VASG-Approved Architecture as a block causes problems 2043 VASG-Approved Numeric VALUE attribute parameter can't have sign 2044 VASG-Approved Deprecation of linkage ports affects boundary scan description language 2045 VASG-Approved Add the ability to comment an entire block of code 2046 Forwarded Type independent ports and subprogram parameters 2047 VASG-Approved Backslash in extended identifiers 2048 VASG-Approved Miscellaneous errors 2049 VASG-Approved Circular definition of an event on a signal 2050 VASG-Approved Definition of S'Last_Value was apparently broken in 1993 2051 VASG-Approved Path_name and instance_name do not allow for protected types 2052 VASG-Approved Path_name and instance_name don't deal with operator symbols 2053 VASG-Approved Minor Typos in VHDL 2002 part 2 2055 VASG-Approved Prohibition on assignment of protected types not normative 2056 VASG-Approved Can an attribute name that denotes a function be used where a name is required? 2057 VASG-Approved Access-typed parameters to predefined "=" and "/=" 2058 VASG-Approved Does USE of type name make operators and literals visible? 2059 VASG-Approved Upper/lower case character mapping is not clear 2060 Forwarded Include truth table for multi-input/multi-output logic. 2061 VASG-Approved Default actions on severity flags is different between simulators 2062 ISAC-Approved Range staticness 2063 Forwarded Unconstrained array formals should not get subtype from actuals 2064 VASG-Approved Type conversion of unconstrained output in a port map 2065 Forwarded OTHERS in aggregates too restrictive 2066 Forwarded Multidimensional array in IEEE Std 1076.6-2004 2067 Forwarded Enhancement: Logical link interface abstraction 2068 VASG-Approved Entity instantiation with space before the entity name 2069 VASG-Approved Visibility of generics in block configurations 2070 ISAC-Approved Support for floating point denormal numbers 2071 VASG-Approved Indexed name in case expression 2072 Forwarded Allow static operations on "ranges" 2073 ISAC-Approved Index constraints and discrete range conversions from universal_integer 2075 ISAC-Approved Ajay Arrays with numeric and enumeration index types are not closely related 2076 Forwarded A member attribute for records 2078 ISAC-Approved Allow attribute declaration/specification in package body 2000 VASG-Approved Where may/must deferred constant declaration appear 2001 VASG-Approved Resize not working in numeric_std.vhd (1076.3 2002 VASG-Approved Resize(R.2) function in numeric_std.vhd does improper array length check 2003 Forwarded Specification of multi-cycle paths 2004 VASG-Approved Definition of SLA doesn't make sense 2005 Duplicate sla operator behavior does not match typical hardware behavior 2006 Forwarded "else" in "if generate"? 2007 Forwarded VHDL needs to be enhanced to allow the modeling of switches. 2008 VASG-Approved Source value of undriven, non-sourced INOUT, OUT or BUFFER port 2009 Forwarded New std package, containing compiler and target identification information 2010 VASG-Approved The description of type/subtype relationship could be better 2011 Forwarded A package body should be able to consist of several files 2012 Forwarded VHDL lacks inherent statements to describe the most basic hardware design equations 2013 VASG-Approved Exact subtype "matching" for port associations 2014 Forwarded Allowance of the keyword "all" in place of a sensitivity list is desirable 2015 Forwarded Generics should be able to incorporate other generics 2016 Duplicate Allowance of the keyword "all" in place of a sensitivity list is desirable 2017 Duplicate Generics should be able to incorporate other generics 2018 VASG-Approved Variable IN parameter should be no different than constant 2019 Forwarded Reading outputs from within architecture 2020 VASG-Approved Keyword REPORT is over-used 2021 Forwarded Dynamic hardware construct 2022 Forwarded Elements of constant composite to be locally static 2023 VASG-Approved Add predefined array types for integer, boolean, real and time 2024 Forwarded VHDL needs encryption support 2025 Forwarded "Generate" for sequential code 2026 Forwarded Upward propagating parameters 2027 Forwarded When loop index is static, drivers are created for each element of array 2028 VASG-Approved Clarify simulation cycle. 2029 VASG-Approved Non-relevant words and paragraph. 2030 VASG-Approved What signature does a method have 2031 VASG-Approved "mod" function needed for TIME 2032 VASG-Approved Function "now" is not pure 2033 Forwarded Incremental operator and auto subtype boundary wrap 2034 Forwarded Introduce history attribute on signals to auto infer registers 2035 Forwarded new function "stages" automates pipelining 2036 VASG-Approved protected_type_declarative_item includes subprogram_specification 2037 VASG-Approved Typo wrt now in the index 2039 VASG-Approved Minor typos 2040 VASG-Approved Problems with OTHERS in aggregates 2041 Forwarded Association of members is too restricted 2042 VASG-Approved Architecture as a block causes problems 2043 VASG-Approved Numeric VALUE attribute parameter can't have sign 2044 VASG-Approved Deprecation of linkage ports affects boundary scan description language 2045 VASG-Approved Add the ability to comment an entire block of code 2046 Forwarded Type independent ports and subprogram parameters 2047 VASG-Approved Backslash in extended identifiers 2048 VASG-Approved Miscellaneous errors 2049 VASG-Approved Circular definition of an event on a signal 2050 VASG-Approved Definition of S'Last_Value was apparently broken in 1993 2051 VASG-Approved Path_name and instance_name do not allow for protected types 2052 VASG-Approved Path_name and instance_name don't deal with operator symbols 2053 VASG-Approved Minor Typos in VHDL 2002 part 2 2055 VASG-Approved Prohibition on assignment of protected types not normative 2056 VASG-Approved Can an attribute name that denotes a function be used where a name is required? 2057 VASG-Approved Access-typed parameters to predefined "=" and "/=" 2058 VASG-Approved Does USE of type name make operators and literals visible? 2059 VASG-Approved Upper/lower case character mapping is not clear 2060 Forwarded Include truth table for multi-input/multi-output logic. 2061 VASG-Approved Default actions on severity flags is different between simulators 2062 ISAC-Approved Range staticness 2063 Forwarded Unconstrained array formals should not get subtype from actuals 2064 VASG-Approved Type conversion of unconstrained output in a port map 2065 Forwarded OTHERS in aggregates too restrictive 2066 Forwarded Multidimensional array in IEEE Std 1076.6-2004 2067 Forwarded Enhancement: Logical link interface abstraction 2068 VASG-Approved Entity instantiation with space before the entity name 2069 VASG-Approved Visibility of generics in block configurations 2070 ISAC-Approved Support for floating point denormal numbers 2071 VASG-Approved Indexed name in case expression 2072 Forwarded Allow static operations on "ranges" 2073 ISAC-Approved Index constraints and discrete range conversions from universal_integer 2075 ISAC-Approved Ajay Arrays with numeric and enumeration index types are not closely related 2076 Forwarded A member attribute for records 2078 ISAC-Approved Allow attribute declaration/specification in package body 2080 ISAC-Approved Chuck Case expression should include parenthesized expression 2081 ISAC-Approved Chuck The term ancestor is used where parent is meantReceived on Wed Mar 15 18:03:20 2006
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