JSAC: slightly revised IR 2091: Translation between std_logic_vector based types and std_ulogic_vector

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VHDL Issue Number:        2091  

Language_Version          VHDL-2002
Classification            Language Definition Problem
Summary                   Translation between std_logic_vector based types and std_ulogic_vector

Relevant_LRM_Sections In std_logic_1164 there is a function called:
                          to_stdlogicvector (std_ulogic_vector) which
                          is used to convert from the base type
                          "std_ulogic" to the base type "std_logic"
                          because the base type for these types are
                          the same, some simulators say they the are
                          interchangeable.  Others do not.

Related_Issues            There were some other issues recently on closely related subtypes.
Key_Words_and_Phrases     to_stdlogicvector, to_stdulogicvector
Authors_Name              David Bishop
Authors_Phone_Number      585-726-6788
Authors_Fax_Number        
Authors_Email_Address     dbishop@vhdl.org
Authors_Affiliation       Eastman Kodak
Authors_Address1          2400 mt read Blvd
Authors_Address2          Rochester NY 14650-3006
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           19 April 2006
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

Please look at the following code:
    library ieee:
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    
    ......
    
    variable UUU :
    unsigned (5 downto 0);
    variable SSS : std_logic_vector (5 downto 0);
    variable SUSU : std_ulogic_vector (5 downto 0);
    begin
      SUSU ::    std_ulogic_vector (SSS);  -- works but shouldn't (use to_stdulogicvector(SSS))
      SSS := std_logic_vector (SUSU);  -- works but shouldn't (use to_stdlogicvector(SUSU))
      UUU := unsigned (sss);   -- works
      SSS := std_logic_vector(UUU); -- works
      UUU := unsigned(SUSU);  -- works but shouldn't (use unsigned(to_stdlogicvector(SUSU)))
      SUSU := std_ulogic_vector(UUU); -- works but shouldn't (use to_stdulogicvector(std_logic_vector(UUU)))
    
Added: the relevant types in package numeric_std are:
   type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
   type SIGNED is array (NATURAL range <>) of STD_LOGIC;

The relevant types in package std_logic_1164 are:

    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
    SUBTYPE std_logic IS resolved std_ulogic;
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;


Proposed Resolution
-------------------

Two as I see it.  

If this is legal VHDL, then a note about closely related subtypes
should be in the LRM.

If this is not legal VHDL, then I will notify the group which says
this code is legal.

So far 1 simulator says this is legal and 3 say it isn't.

VASG-ISAC Analysis & Rationale
------------------------------
TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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