Larry submitted this a little while ago and somehow I lost it. I think that its already been covered by IR2039. VHDL Issue Number: 2102 Language_Version VHDL-2002 Classification LRM Examples, Notes and Appendices Summary Typo in Section 3.2.1. Example Relevant_LRM_Sections 3.2.1.1 Related_Issues Key_Words_and_Phrases Authors_Name Larry Soule Authors_Phone_Number 650-584-1919 Authors_Fax_Number Authors_Email_Address larrys@synopsys.com Authors_Affiliation Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 23 June 2006 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- The example at the end of section 3.2.1.1 has a typo or two in the generic map. The text currently has generic map(1 to 2 : > (others => '0')) I believe this has two errors. First the formal name is missing so the first part should be "ROM(1 to 2)". The second problem is that ROM(1 to 2) is of type Memory which is an unconstrained array of WORD (basically a bit-vector) so the type of the actual should be an array of WORD Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------Received on Thu Aug 17 17:32:45 2006
This archive was generated by hypermail 2.1.8 : Thu Aug 17 2006 - 17:32:46 PDT