RE: ISAC: New IR 2104 Using a configuration to leave a design unbound

Jim,

12.4.3 says, "Elaboration of a component instantiation statement that
instantiates a component declaration has no effect unless the component
instance is either fully bound to a design entity defined by an entity
declaration and architecture body or bound to a configuration of such a
design entity."

So a design in which the binding of the component instance is deferred
effectively has a hole in the design hierarchy. I believe this is what you
are looking for.

The case of finding an entity of the same name as the component is covered
under the default binding rules. The LRM specifies when they come into play,
and it is only when no binding indication is specified. Including a binding
indication with an entity aspect of "open" prevents application of the
default binding.

Hope this clarfies things.

Cheers,

PA

--
Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
PO Box 640                    VoIP: sip://0871270078@sip.internode.on.net
Stirling, SA 5152             Phone (mobile):  +61 414 70 9106
Australia


> -----Original Message-----
> From: owner-isac@server.eda.org 
> [mailto:owner-isac@server.eda.org] On Behalf Of Jim Lewis
> Sent: Wednesday, 15 November 2006 13:19 PM
> To: isac@server.eda.org
> Subject: Re: ISAC: New IR 2104 Using a configuration to leave 
> a design unbound
> 
> 
> Peter,
>  From 5.2.1.1:
>     The third form of entity aspect is used to specify that the
>     identification of the design entity is to be deferred.
>     In this case, the immediately enclosing binding indication is
>     said to not imply any design entity. Furthermore,
>     the immediately enclosing binding indication must not include a
>     generic map aspect or a port map aspect.
> 
> 
> What does "deferred" mean?  Does it mean don't ever bind this 
> design? Or does it mean if there is a visible entity of the 
> name MEMIO in the library, then feel free to default bind it?
> 
> I need the semantic, "don't ever bind this design".
> 
> Cheers,
> Jim
> 
> > Chuck,
> > 
> > Looks like Jim overlooked the use of the word open in a binding 
> > indication to defer binding of a component. Analyzed IR attached.
> > 
> > Cheers,
> > 
> > PA
> > 
> > --
> > Dr. Peter J. Ashenden         peter@ashenden.com.au
> > Ashenden Designs Pty. Ltd.    www.ashenden.com.au
> > PO Box 640                    VoIP: 
> sip://0871270078@sip.internode.on.net
> > Stirling, SA 5152             Phone (mobile):  +61 414 70 9106
> > Australia
> > 
> > 
> >> -----Original Message-----
> >> From: owner-isac@server.eda.org
> >> [mailto:owner-isac@server.eda.org] On Behalf Of Chuck Swart
> >> Sent: Wednesday, 15 November 2006 4:27 AM
> >> To: isac@server.eda.org
> >> Subject: ISAC: New IR 2104 Using a configuration to leave a 
> >> design unbound
> >>
> >>
> >> this IR is also in the data base.
> >>
> >>
> >>
> 
> 
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training             mailto:Jim@SynthWorks.com
> SynthWorks Design Inc.           http://www.SynthWorks.com
> 1-503-590-4787
> 
> Expert VHDL Training for Hardware Design and Verification 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>