ISAC: analysis of IR 2105

Also please review IR 2099 for next week's meeting.

Chuck Swart

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VHDL Issue Number:        2105

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Can't declare an alias of a character literal without using expanded name
Relevant_LRM_Sections     4.3.3, 6.1
Related_Issues            
Key_Words_and_Phrases     alias, character literal
Authors_Name              Peter Ashenden
Authors_Phone_Number      +61 414 709 106
Authors_Fax_Number        
Authors_Email_Address     peter@ashenden.com.au
Authors_Affiliation       Ashenden Designs
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Analyzed

Superseded By:

------------------------
Date Submitted:           7 December 2006
Date Analyzed:            03 January 2007
Author of Analysis:       Chuck Swart
Revision Number:          1
Date Last Revised:        03 January 2007

Description of Problem
----------------------

The syntax rules prevent a character literal being used by itself as
the name in an alias declaration. For example, it is not legal to
write
    
      alias low is '0'[return bit];
    
    The rule for name in 6.1 allows a simple name or an operator
    symbol, but not a character literal. The above would have to be
    written using an expanded name, such as
    
      alias low is STANDARD.'0'[return bit];
    
    since the suffix of an expanded name can be a character literal.
    
    Similarly, the following is illegal:
    
      type T is ('a', 'b', 'c');
      alias 'A' is 'a'[return T];
    
    Assuming this was in an enclosing regional named R, the alias would have to be written as
    
      alias 'A' is R.'a'[return T];

Proposed Resolution
-------------------

Augment the BNF rule for name in 6.1 to include character_literal as
an alternative. This would mirror other places where simple_name and
operator_symbol are alternatives for a designator (such as in the
entity tag of an attribute specification).

VASG-ISAC Analysis & Rationale
------------------------------

It seems strange that a suffix in a syntactic selected name can be a
character literal but that a character literal is not allowed as a
name. This appears to be an oversight which goes all the way back to
VHDL-1987, since the Ada grammar from which it was derived allows
character literals as names. Some simple tests indicate that the
grammar is not made more complex by adding the proposed BNF rule for
"name" in 6.1.

Since the proposed change increases usability, improves uniformity
and does not impose significant implementation burdens, the ISAC
recommends that the proposal be accepted.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

Technically, the VHDL-2002 version of the language is clear: character
literals are not allowed as names. However, since this was evidently
an oversight, the LRM should be interpreted as if the changes for
future revisions were in effect.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

In clause 6.1 and in the annex containing the syntax summary replace
the production

name ::=
     simple_name
   | operator_symbol
   | selected_name
   ...

with

name ::=
     simple_name
   | operator_symbol
   | character_literal
   | selected_name
   ...




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