Attached is another analysis of IR 2099. This analysis was previously sent to John Ries and to Peter. Peter hasn't commented yet. John has suggested that we might need a more refined set of rules. Basically there are four cases to consider when dealing with rules prioritizing explicit declarations over implicit declarations: 1) an implicit alias of an implicitly declared operator. 2) an implicit alias of an explicitly declared operator (see case 5). 3) an explicit alias of an implicitly declared operator. 4) an explicit alias of an explicitly declared operator. We need to decide if such a refinement is necessary, and if so, what the priorities are. Chuck Swart -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------BEGINNING OF IR---------------- VHDL Issue Number: 2099 Language_Version VHDL-2002 Classification Language Definition Problem Summary Alias declarations introduce homographs Relevant_LRM_Sections 4.3.3.2 Nonobject aliases 10.3 Visibility Related_Issues Key_Words_and_Phrases nonobject aliases, homographs Authors_Name Peter Ashenden Authors_Phone_Number +61 414 709 106 Authors_Fax_Number Authors_Email_Address peter@ashenden.com.au Authors_Affiliation Ashenden Designs Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Analyzed Superseded By: ------------------------ Date Submitted: 14 June 2006 Date Analyzed: 26 September 2006 Author of Analysis: Chuck Swart Revision Number: 6 Date Last Revised: 07 February 2007 Description of Problem ---------------------- This issue was originally raised by John Ries in the Accellera VHDL-TC review of P1076-2006/D2.11 and entered as Bugzilla bug #44. Because it treats issues with VHDL-2002 it has been entered as an ISAC IR. On page 114 in nonobject alias it states : c) If the name denotes an enumeration type or a subtype of an enumeration type, then one implicit alias declaration for each of the literals of the base type immediately follows the alias declaration for the enumeration type; each such implicit declaration has, as its alias designator, the simple name or character literal of the literal and has, as its name, a name constructed by taking the name of the alias for the enumeration type or subtype and substituting the simple name or character literal being aliased for the simple name of the type or subtype. Each implicit alias has a signature that matches the parameter and result type profile of the literal being aliased. d) Alternatively, if the name denotes a subtype of a physical type, then one implicit alias declaration for each of the units of the base type immediately follows the alias declaration for the physical type; each such implicit declaration has, as its alias designator, the simple name of the unit and has, as its name, a name constructed by taking the name of the alias for the subtype of the physical type and substituting the simple name of the unit being aliased for the simple name of the subtype. e) Finally, if the name denotes a type or a subtype, then implicit alias declarations for each predefined operator operation for the type immediately follow the explicit alias declaration for the type or subtype and, if present, any implicit alias declarations for literals or units of the type. Each implicit alias has a signature that matches the parameter and result type profile of the implicit operation being aliased. What happens if there is a homograph already declared or aliased? For example (this is case 3 in the analysis section) type my_logic is ( '0', '1', 'X', 'Z'); function "="( a, b: my_logic) return boolean; alias alt_logic is my_logic; -- the following alias are implicit alias '0' is '0' [ return my_logic]; alias '1' is '1' [ return my_logic]; alias 'X' is 'X' [ return my_logic]; alias 'Z' is 'Z' [ return my_logic]; alias "/=" is "/=" [ my_logic, my_logic, return boolean]; alias "=" is "=" [ my_logic, my_logic, return boolean]; -- note implicit "=" not explicit one. It seams to me that all the alias are homographs. In all cases except the "=" these aliases denote the exact same objects so is this an error?. In the case of "=" these are different functions the alias is to the predefined "=" and there is an explicit "=" already declared. Is this an error? What happens if the explicit "=" is declared after the alias? This also raises the question, after I declare an alias to a type is it legal to define an explicit version of a predefined operator on the aliased type? For example (this is case 4a in the analysis section) library ieee; package mycompare is alias std_logic is ieee.std_logic_1164.std_logic; -- there is an implicit alias alias "=" is ieee.std_logic_1164."="[ieee.std_logic_1164.std_ulogic, ieee.std_logic_1164.std_ulogic, return ieee.std_logic_1164.std_ulogic]; -- Is this legal?? function "=" ( a, b : std_logic) return boolean; .... Does clause 10.3 statement Two declarations that occur immediately within the same declarative region, other than the declarative region of a block implied by a component instantiation or the declarative region of a generic-mapped package or subprogram equivalent to a package instance or a subprogram instance,28 must not be homographs, unless exactly one of them is the implicit declaration of a predefined operation. In such cases, a predefined operation is always hidden by the other homograph. Apply here? This needs to be resolved because the numeric_std package defines two aliases to types. They are alias U_UNSIGNED is UNRESOLVED_UNSIGNED; and alias U_SIGNED is UNRESOLVED_SIGNED; Since the meaning of this is unclear, the LRM needs to either remove the aliases from the package or define the behavior Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ It would appear that the rules for nonobject aliases were written under the assumption that the name being aliased is declared in a different declarative region. The example in the LRM illustrates that, with the name BIT being declared in STD.STANDARD. Aliasing a name declared in the same declarative region as the aliased declaration introduces the issues the submitter raised. There are several cases for which the LRM seems overly restrictive. Here are some of the cases which need to be covered (including the submitter's examples): case 1a: package p_test is type my_logic is ( '0', '1', 'X', 'Z'); alias alt_logic is my_logic; end package p_test; case 1b: package p_test is type my_logic is ( a, b, c, d); alias alt_logic is my_logic; end package p_test; This is case 1a with the enumeration literals changed to avoid clouding the issue with bit and character literals. This declares, among other things: "="[my_logic, my_logic return boolean] and "="[alt_logic, alt_logic return boolean] The issues are: Is this code legal and, if so, is an expression like a = b now ambiguous? case 2: package p_test is alias std_logic1 is ieee.std_logic_1164.std_logic; alias std_logic2 is ieee.std_logic_1164.std_logic; end package p_test; case 3: package p_test is type my_logic is ( '0', '1', 'X', 'Z'); function "="( a, b: my_logic) return boolean; alias alt_logic is my_logic; end package p_test; case 4a: package p_test is type my_logic is ( '0', '1', 'X', 'Z'); alias alt_logic is my_logic; function "="( a, b: my_logic) return boolean; end package p_test; case 4b: package p_test is type my_logic is ( '0', '1', 'X', 'Z'); alias alt_logic is my_logic; function "="( a, b: alt_logic) return boolean; end package p_test; case 5: package p1 is function "=" (a,b: ieee.std_logic_1164.std_logic ) return boolean; ... end package p1; package p_test is use work.p1.all; ... alias std_logic is ieee.std_logic_1164.std_logic; end package p_test; CASE 6: package p1 is type my_logic is ( '0', '1', 'X', 'Z'); end package p1; package p2 is use p1.all; alias alt_logic is my_logic; function "="( a, b: my_logic) return boolean; end package p2 Under current rules the implicit alias to "="[my_logic, my_logic, return boolean] does occur so now we have two conflicting declarations. However, this code should be legal. CASE 7: package p1 is type my_logic is ( '0', '1', 'X', 'Z'); end package p1; package p2 is use p1.all; alias alt_logic is my_logic; end package p2; package p4 is use p1.all; use p2.all; constant C : alt_logic := 'X'; end package p4; It isn't clear whether this is legal or illegal under the VHDL-200X interpretation which allows explicit declarations to hide implicit declarations. CASE 8: package p1 is type my_logic is ( '0', '1', 'X', 'Z'); end package p1; package p2 is use p1.all; alias alt_logic is my_logic; end package p2; package p3 is use p1.all; alias other_logic is my_logic; end package p3; package p4 is use p3.all; use p2.all; constant C : alt_logic := 'X'; end package p4; This case appears to be illegal under current and D3.0 rules. However, this code should be legal. CASE 9: package p1 is type T is (a,c,c); alias "=' is "="[T,T return boolean]; function '=' ( L,R : T) return boolean; end package p1; This case is illegal because it contains two homographs declared in the same declarative regions. Since there is no reasonable way to disambiguate expressions like a = b, this code should still be illegal under the proposed language change. Analysis: Clearly, it is highly desirable that several of the cases be legal, and that implied aliases not introduce needless expression ambiguity. The ISAC considered two possible approaches to resolving this issue. The first approach is to add additional cases to Clause 10.4 to cover various implicit/explicit combinations introduced by implicit aliases. The second is to reword the LRM so that two principles hold: Principle 1: An alias of a declaration is not a homograph of that declaration and, in addition, two alias declarations of the same designator that denote the same named entity are not homographs. The two declarations are viewed as if they were multiple references to the same named entity. So nonobject aliases have more of a flavor of USE clauses than of object declarations. Principle 2: An alias of an implicitly predefined operation is itself considered to be an implicitly predefined operation, so that explicitly declared overloaded operators will take precedence in use clauses. This principle holds whether or not the alias itself is implicitly declared. The second approach appears to be the most intuitive and offers the greatest flexibility to the language user. This approach provides the following analysis of the various cases: For case 1a, the implicit declarations of aliases of the enumeration values are not homographs of the original declaration. Therefore, case 1 is legal and the expression a = b is not ambiguous. For case 1b, the case is legal, and the expression a = b is not ambiguous. Since both "=" declarations denote the same function. For case 2, the implicit declarations associated with each alias are not homographs. Therefore, case 2 is legal. Case 3. Principle 2 implies that the explicitly declared "=" function hides the alias of the implicit function "=" associated implicitly with the alias alt_logic This implicit "=" function is a homograph of the explicitly declared "=" function. Case 3 is legal, and the explicitly declared "=" is visible. Case 4a. It is legal to overload the implicitly declared "=" operator associated with the alias alt_logic. Case 4a is legal, and the explicitly declared "=" is visible after its declaration. Case 4b. Since alt_logic is an alias for my_logic, Case 4b is the same as case 4a. Case 5. (VHDL-200X interpretation) Clause 10.4 Implies that a potentially visible explicit declaration overrides a visible implicit declaration. Therefore, by Principle 2, Case 5 is legal and the overloaded "=" operation from package p1 is visible in package p_test. Case 6. The explicit "=" operation overrides the implicit one from package p1. Case 6 is legal and the explicitly declared "=" from package p2 is visible. Case 7. Each package provides a potentially visible alias of 'X', but since both aliases refer to the same declaration, they are not homographs. Case 7 is legal. Case 8. The implicit aliases in all packages refer to the same declaration of 'X'. Case 8 is legal. Case 9. Two homographs are declared in the same declarative region. Since neither is an implicit declaration or an implicit alias, this code is illegal. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- The resolution of the various cases is not clear for VHDL-2002, and may conceivably vary between implementations. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Make the following changes to D3.0: Clause 10.3 Visibility Change: "-- The visibility rules determine more than one possible meaning, In such a case, the occurrence of the identifier is legal at this point if and only if exactly one visible declaration is acceptable for the overloading rules in the given context." To: "-- The visibility rules determine more than one possible meaning. In such a case, the occurrence of the identifier is legal at this point if and only if either exactly one visible declaration is acceptable for the overloading rules in the given context or all visible declarations denote the same named entity." Add to: "If overloading is allowed for both declarations, then each of the two is a homograph of the other if they have the same identifier, operator symbol, or character literal, as well as the same parameter and result type profile (see 3.1.1)" ",except that declarations that denote the same named entity are not homographs." Replace: "Two declarations that occur immediately within the same declarative region,...,must not be homographs, unless exactly one of them is the implicit declaration of a predefined operation." with "Two declarations that occur immediately within the same declarative region,...,must not be homographs, unless exactly one of them is the implicit declaration of a predefined operation or is an implicit alias of such an implicit declaration." Replace: "In such cases, a predefined operation is always hidden by the other homograph." With: "In such cases, a predefined operation or alias thereof is always hidden by the other homograph." Clause 10.4 Use clauses Replace "a) A potentially visible implicit declaration of a predefined operation is not mode directly visible if the place considered is within the scope of an explicitly declared homograph of that implicit declaration." with "a) A potentially visible implicit declaration of a predefined operation or an implicit alias of such a declaration is not made directly visible if the place considered is within the scope of an explicitly declared homograph of that implicit declaration or the implicit alias." -------------END OF IR----------------Received on Thu Mar 1 16:23:22 2007
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