Draft analysis for IR1000 (at last)

Folks,

Attached is my draft analysis of IR1000, covering miscellaneous typos and
minor definitional issues. Most of the items have already been addressed in
VHDL-2002. A small number remain to be fixed in VHDL-2007.

Sorry it took so long to get around to this.

Cheers,

PA

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Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
PO Box 640                    VoIP: sip://0871270078@sip.internode.on.net
Stirling, SA 5152             Phone (mobile):  +61 414 70 9106
Australia

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