ISAC: Analysis of IR 2112 (note correct number this time!)

Peter has provided the analysis for this.

Chuck


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VHDL Issue Number:        2112

Language_Version          VHDL-2002
Classification            Language Definition Problem
Summary                   Can attributes be applied to a signal on the entity within the 
                          architecture for that entity?
Relevant_LRM_Sections     VHDL LRM (2002) and in the section 4.4 (Attribute declarations)
Related_Issues
Key_Words_and_Phrases
Authors_Name              Kevin Jennings
Authors_Phone_Number      734-737-4268
Authors_Fax_Number        734-737-4740
Authors_Email_Address     Kevin.Jennings@Unisys.com
Authors_Affiliation       Unisys
Authors_Address1          41100 Plymouth Road
Authors_Address2          Plymouth, Michigan 48170
Authors_Address3

Current Status:           Analyzed

Superseded By:

------------------------
Date Submitted:           28 March 2007
Date Analyzed:            31 March 2007
Author of Analysis:       Peter Ashenden
Revision Number:          1
Date Last Revised:        31 March 2007

Description of Problem
----------------------

Below I've attached some VHDL code where a particular signal on the
entity (za_data) has an attribute defined for it in the architecture
for that entity.  This code is being handled correctly by both
Modelsim (6.2c) and Quartus (6.1) but Synplify 8.8 spits out a warning
(also pasted below) which essentially says that the attribute
declaration must be put in the entity, not in the architecture.

I've opened a service request to Synplify about this back in September
2006 and just recently.  Back in September, the folks at Synplicity
agreed that this was a bug and they would fix it in the next release.
The next release (8.8) came out, I tried it and saw that the problem
has not been fixed so I opened another service request.  Now they are
saying that this 'seems to' not be a bug.  So, per the LRM, is it a
bug or isn't it?

 The short version synopsis of the code is something like

    entity sdram_0 is
            port (
            ...
                     signal za_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
            ...
                  );
    end entity sdram_0;


    architecture europa of sdram_0 is
        ...
    attribute ALTERA_ATTRIBUTE : string;
    attribute ALTERA_ATTRIBUTE of za_data : signal is "FAST_INPUT_REGISTER:    ON";

    begin
        ...
    end europa;

    ---- Start of warning message ----
    No such identifier, za_data, of proper type in current declarative region
    ---- End of warning message ----



Proposed Resolution
-------------------

I'd just like a clarification on the issue.

VASG-ISAC Analysis & Rationale
------------------------------

Subclause 5.1 of IEEE 1076-2002 states:

  "... an attribute specification for an attribute of an interface
  object of a design unit, subprogram, or block statement must appear
  immediately within the declarative part of that design unit,
  subprogram, or block statement."

A port of an entity is an interface object of the entity, and so any
attribute specification decorating the port must appear immediately
within the declarative part of the entity. The declarative part of an
entity is defined in the syntax rules for an entity in subclause 1.1,
and does not include the text of any architecture body associated with
that entity. It is possible that the submitter is confusing the
declarative part of the entity with the declarative region, which does
extend to the architecture.

Thus, the submitter's code is incorrect. The attribute specification
should appear immediately within the entity declarative part.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

No change.


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