-- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. VHDL Issue Number: 2113 Language_Version VHDL-93 Classification Language Definition Problem Summary FILE Input and ROM Inference Relevant_LRM_Sections VHDL Register Transfer Level (RTL) Synthesis 1076.6 Related_Issues Key_Words_and_Phrases Authors_Name Amal Khailtash Authors_Phone_Number +1 (613) 271-1101 x.2271 Authors_Fax_Number Authors_Email_Address Amal.Khailtash@edgewater.ca Authors_Affiliation Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 16 April 2007 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- Often you would like to code a ROM using constants that are read from a file. Most synthesis tools do not support FILE I/O. Proposed Resolution ------------------- It would be nice to add a feature to VHDL Register Transfer Level (RTL) Synthesis 1076.6 to support FILE I/O used in functions/procedures as long as they return a constant value. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBDReceived on Mon Apr 16 10:53:16 2007
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