Attached are copies of these new IRs. They are also available on the website. Chuck Swart 2115 Submitted Binding specification should be binding indication 2116 Submitted What is the direction of std_logic_vector & '0' 2117 Submitted Block comment is not there in vhdl 2118 Submitted Typo in 9.2 Note 2 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. VHDL Issue Number: 2115 Language_Version VHDL-2002 Classification LRM Terminology, Grammar and Typographical Errors Summary Binding specification should be binding indication Relevant_LRM_Sections 10.3 Visibility Annex B Glossary Related_Issues Key_Words_and_Phrases Authors_Name James Unterburger Authors_Phone_Number 503-685-0860 Authors_Fax_Number Authors_Email_Address jamesu@model.com Authors_Affiliation Mentor Graphics Authors_Address1 8005 SW Boeckman Rd. Authors_Address2 Wilsonville, OR 97070 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 16 May 2007 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- The term "binding specification" appears twice in the LRM. The correct wording should be "binding indication". The locations are 10.3, item l (ell) in the list, and B.126 ("imply") in the glossary. These are duplicated in the proposed 200X LRM (D3.0) at 10.3 item m (em) in the list, and B.179 ("imply") in the glossary. Proposed Resolution ------------------- Change "binding specification" to "binding indication" at the two places. And fix the 200X proposed LRM as well. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD VHDL Issue Number: 2116 Language_Version VHDL-2002 Classification Language Definition Problem Summary What is the direction of std_logic_vector & '0' Relevant_LRM_Sections 7.2.4 Related_Issues Key_Words_and_Phrases Authors_Name Larry Authors_Phone_Number Soule Authors_Fax_Number Authors_Email_Address larrys@synopsys.com Authors_Affiliation Synopsys Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 25 May 2007 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- The issue is with the code below signal S : std_logic_vector(6 downto 0); ... S & '0' ; What is the type of the expression "S & '0'"? The table in Section 7.2.4 says if the left operand type is "any one-dimensional array type" and the right operand type is "the element type", then the result type is "Same array type". The way I read this is that the result should be of the same type as S -- the left operand. That is, std_logic_vector with a downto range. The other way to read it is that the "same array type" is just std_logic_vector which defaults to a "to" range. However, B.15 defines "array type" as including the index range. If it matters, this expression is then used as a parameter to a function which takes an unconstrained array type: function f(inp : std_logic_vector; size : integer), but I believe the input parameter just inherits the bounds and direction of what was passed in. Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD VHDL Issue Number: 2117 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary Block comment is not there in vhdl Relevant_LRM_Sections Related_Issues Key_Words_and_Phrases Authors_Name sudeep Authors_Phone_Number 91-9911518886 Authors_Fax_Number Authors_Email_Address sudeepts@gmail.com Authors_Affiliation Authors_Address1 E-231, 1st floor, sec-27, Noida. Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 29 May 2007 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- Please provide an option for block comment in vhdl-200 unlike in vhdl there is only line comment, like other languages verilog, and vera, vhdl should have block comments. Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD VHDL Issue Number: 2118 Language_Version VHDL-2002 Classification LRM Examples, Notes and Appendices Summary Typo in 9.2 Note 2 Relevant_LRM_Sections 9.2 Note 2 Related_Issues Key_Words_and_Phrases Authors_Name Paul Butler Authors_Phone_Number 512 683 8743 Authors_Fax_Number Authors_Email_Address Paul.Butler@ni.com Authors_Affiliation National Instruments Authors_Address1 11500 N. Mopac Authors_Address2 Austin, TX 78759 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 5 June 2007 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- In the LRM section 9.2, Note 2 (page 135) refers to section 2.6.4, but the LRM doesn't contain a section with that number. Proposed Resolution ------------------- I believe that's a mistaken reference that should read, "see 12.6.4". VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBDReceived on Mon Jun 18 14:56:03 2007
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