ISAC: Minutes from meeting on 02 August 2007

The minutes are also available at eda.org
Chuck Swart

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Minutes of ISAC meeting held via telecom on 02 August 2007

Present: Peter Ashenden, Larry Soule, Chuck Swart, Lance Thompson, Ajay Verikat

Absent: Jim Lewis

Next Meeting Thursday, September 06, 2007, 8 pm Pacific Daylight Time
             (Friday, September 07, 2007, 3 am GMT)

TOPIC: IR 2119 Can't declare a protected type and object of that type
in a single package

There are several additional situations in VHDL in which a item
declared in a package header cannot be freely referenced later in the
header. Examples include deferred constants and subprogram
declarations.  Since a protected type declared in a package header can
be referenced in other packages (both header and body) and in other
declarative regions, unless a persuasive use case is presented, there
seems to be little need to change the language semantics to allow the
requested extension.

ACTION: Peter to analyze.

TOPIC: IR 1070 VPI Issue 14 -- Prefixes in USE clauses

No progress.

ACTION: Peter to update analysis.

TOPIC: IR 2099 Alias declarations introduce homographs

The discussion centered around example 9a:

  package p1 is
     type T is (a,b,c); -- 1. implicit declaration "="[T,T return boolean]
     alias "=" is "=" [T,T return boolean]; -- 2. aliased operator is implicit "=" from 1
     function "=" ( L,R : T) return boolean; -- 3. explicit declaration of "="
  end package p1;

The proposed changes would make (2) and (3) illegal. Ajay offered the
consideration that principle 1 says:

     "...The two declarations are viewed as if they 
     were multiple references to the same named entity. ..."

Furthermore, he suggests:

If both (1) and (2) refer to the same named entity, and the situation
described here is legal in the absence (2), why should the presence of
(2) make this illegal?

Peter offered the following counter analysis. (3) and (1) are legal
together because explicit declarations override implicit
declarations. This particular application of the rule is necessary
because the implicit operations often do not provide the desired
results.  However, (2) and (3) are both explicit declarations. This is
a very unusual situation, and could well be a mistake on the part of
the code writer. Therefore, it should be illegal, and the proposed LRM
wording should not be changed in this area.

Peter's analysis seems persuasive and is accepted by the ISAC. Chuck
will add comments to this example, so that the VASG can consider the
alternative interpretation. He will also incorporate some previous
issues raised by Peter.

ACTION: Chuck to update analysis, all to vote. 

ITEM: IR 2110 Implicit subtype conversions not defined

No progress.

ACTION: Chuck to analyze.

ITEM: IR 2116 What is the direction of std_logic_vector & '0'

Peter's analysis is accepted. The issue is ISAC approved.

ACTION: Chuck to forward to VASG.

ITEM: IR 2117  Block comment is not there in vhdl

This item is technically forwarded to a requirements group, but it has
been noted that the feature has already been added to D3.0.

ACTION: Chuck to inform submitter.

ITEM: IR2118 Typo in 9.2 Note 2

This was incorrectly marked as Superseded. Instead it is a Duplicate

ACTION: Chuck to update.

ITEM: Review of pre-2002 IRs:

1089  Resolved
1090  Resolved
1091  Open
1098  Open
1104  Open
1105  Open
1106  Open
1107  Open
1108  Open
1109  Open
1110  Open
1116  Resolved
1118  Open
1119  Open
1120  Open

ITEM: Action on open pre-2002 IRs.

Chuck will enter them into Bugzilla.  The ISAC will work on them as
low priority.

ACTION: Chuck to enter open IRs into Bugzilla.