ISAC: New IR 2121 Allow for vectors to have assigns and opens in the port map

Attached is the new IR 2121. We can discuss this at next Thursday's meeting.

One issue to think about is the effect of a complicated aggregate on 
partial initialization.
(I have not had much luck researching this IR. The current rule seems to 
have entered VHDL93
without a corresponding IR. The annotation is something like 
"Vallenga/10" which is a ballot
response, probably long since lost.)

After the upcoming meeting, I would like us to consider moving our 
meeting day to Wednesday.

Chuck Swart



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VHDL Issue Number:        2121

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Allow for vectors to have assigns and opens in the port map
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              Kevin Jennings
Authors_Phone_Number      734-737-4268
Authors_Fax_Number        
Authors_Email_Address     Kevin.Jennings@Unisys.com
Authors_Affiliation       Unisys
Authors_Address1          41100 Plymouth Road
Authors_Address2          Plymouth, Michigan 48170 USA
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           31 August 2007
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

Any chance of changing the rule that requires an entire vector to be
assigned in a port map instead of being able to leave some of them
open?  Something like the following....
    
    U1 :
    Some_Device port map( 
         Some_Bus(15 downto 0) :    > Some_Signal, 
         Some_Bus(31 downto 16) => open); 
    
Where I run into this as an issue is generally when I use a VHDL
netlist produced by a CAD program as part of a simulation model.  If
the spec for the physical part indicates that unused pins can (or
sometimes 'should be') left open and the PCBA design is not using the
entire bus than those unused pins on the physical part will be left
with no connection (which is correct per design) but the resulting
VHDL model complains when compiled because the 'Some_Bus' pins must
either all be assigned or all left open.
    
In certain situations, there are some simple work arounds (mentioned
below) but if the language handled the above mentioned port map (which
reflects the reality of the desired PCBA design) things would be much
cleaner.  The model would also not have the situation dependent
drawbacks associated with each of the work arounds.
    
    - Work around #1: If the PCBA design itself is stable and not
    changing, then simply edit the VHDL model for the offending
    schematic pages and move on.
    
    - Work around #2: If the PCBA design is still evolving then see if
    it's possible to get a resistor on to the schematic to drive the
    'unused' pins.
    
    Kevin Jennings

Proposed Resolution
-------------------

See what I listed in the description

VASG-ISAC Analysis & Rationale
------------------------------
TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD