This IR has also been copied to the website. Chuck Swart -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. VHDL Issue Number: 2128 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary Shared Variable declarations in generate? Relevant_LRM_Sections 4.3.1.3 Related_Issues Key_Words_and_Phrases Authors_Name Jim Lewis Authors_Phone_Number 503-590--4787 Authors_Fax_Number Authors_Email_Address jim@synthworks.com Authors_Affiliation Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 13 January 2008 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- Paragraph 2 of 4.3.1.3 contains the following: "Variables declared immediately within entity declarations, architecture bodies, packages, package bodies, and blocks must be shared variables." Proposed Resolution ------------------- Can shared variables be declared in a generate block declarative region? It would seem yes as it is a block declarative region which is also shared by a block statement, however, then the referenced sentence of 4.3.1.3 should also list generate statements. Going further why don't we have a term for declarative regions of constructs that contain concurrent statements (as this would seem to be a term that could be referenced numerous times). And a separate term for declarative regions of constructs that contain sequential statements (processes, subprograms, and protected types). VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBDReceived on Mon Jan 14 11:35:05 2008
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