RE: IRs 2124 and 2126 have been ISAC-Approved

Folks,

Sorry to bring this up after ISAC approval of IR2124, but...

While doing the LRM edits, I realized that the revised wording inadvertently
introduced a constraint on ordering of callbacks. In 12.6.4.2, the revision
of substeps 3) and 4) of step h) result in all vhpiCbTimeOut and
vhpiCbRepTimeOut callbacks being executed after all process executions and
associated callbacks. Originally, the timeout callbacks were executed along
with processes (though between resume and suspect callbacks).

In the spirit of relaxing the ordering, I've revised the revised text as
follows:

h) 3) Each registered and enabled vhpiCbTimeOut and vhpiCbRepTimeOut
      callback whose triggering condition is met is executed. For each
      nonpostponed process P that has resumed in the current simulation
      cycle, the following actions occur in the indicated order:

      -- [as before]

   4) [old step 6) renumbered]

This has the effect of allowing timeout callbacks to be executed in parallel
with processes and their associated callbacks.

I hope this is ok. Please say if there are any reservations about the
change.

Cheers,

PA
--
Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
PO Box 640                    VoIP: sip://0871270078@sip.internode.on.net
Stirling, SA 5152             Phone: +61 8 7127 0078
Australia                     Mobile: +61 414 70 9106
 

> -----Original Message-----
> From: owner-isac@server.eda.org 
> [mailto:owner-isac@server.eda.org] On Behalf Of Chuck Swart - MTI
> Sent: Thursday, 27 March 2008 09:24
> To: isac@server.eda.org
> Subject: IRs 2124 and 2126 have been ISAC-Approved
> 
> 
> IR 2124 has been approved with no changes, following Ajay's email.
> 
> IR2126 has three small changes: 1)The last paragraph of the 
> analysis now correctly refers to clause 7.2.4 instead of 
> clause 7.2.3. 2) the first 
> paragraph
> under "VASG-ISAC Recommendation for Future Revisions notes 
> that there may be additional changes for VHDL-200X. 3) The 
> new list of complete 
> contexts
> in Clause 10.5  changed "the expression in a generate specification 
> (D4.0)" to
> "The expression in a generate statement label used in an external
>   name (D4.0)" which is accurate with respect to D4.0, but 
> might need a 
> slight
> rewording for the final IEEE version.
> 
> With approval of these IRs, the only thing on the ISAC plate for 
> VHDL-200X is
> to finish IR 2123, which we expect to do within a few days.
> 
> Chuck Swart
> 
> 
> 
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