ISAC: New IR 2130 Ability to overload the assignment operator := would be useful

This is a very interesting request, but we probably won't get to it 
until after VHDL-200X is completed.



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VHDL Issue Number:        2130

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Ability to overload the assignment operator := would be useful
Relevant_LRM_Sections     
Related_Issues            I apologise if this is already tabled for the current round of VHDL enhancements.
Key_Words_and_Phrases     assignment, variable assignment, signal assignment, type conversion, operator overloading
Authors_Name              Jonathan Bromley
Authors_Phone_Number      +44 7713 241838
Authors_Fax_Number        
Authors_Email_Address     jonathan.bromley@doulos.com
Authors_Affiliation       
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           17 May 2008
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

Many usability issues with VHDL are related to the perceived
inconvenience of needing to do many type conversions.  Overloading of
the assignment operator :: would permit user- (or package-) defined
automation of many common type conversions.  It would also allow the
automatic resizing of vector results to fit their assignment target.
This latter ability would evidently be a major enhancement to the
usability of the new fixed-point arithmetic package.

Proposed Resolution
-------------------

Permit overloading of variable assignment ::     as:
    
    procedure ":=" ( 
      output <some_type> target; 
      input <some_type> source_expression
    );
    
The signal assignment operator would need to be redefined as a
variable assignment to an implicit variable of the same subtype as the
target signal, followed by signal update using the current signal
assignment semantics.
    
Within the body of a ":=" procedure it might be necessary to appeal to
the built-in definition of ":=".  This should be available as
procedure std.standard.":=" with the existing pre-defined behaviour.
    
In various places in the language, an implied copy operation is
performed.  Obvious examples include passing an actual expression to a
subprogram's formal input parameter; I'm sure there are many others.
In all such situations, the overloaded ":=" operator should be
applied.  In particular, the use of any expression as the test in an
"if" statement should be treated as assignment of the expression to an
implicit boolean variable.  This would permit a consistent approach to
the use of non-Boolean expressions as "if" test expressions.

VASG-ISAC Analysis & Rationale
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TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
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TBD

VASG-ISAC Recommendation for Future Revisions
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TBD