ISAC: New IR 2133 Not locally static expression is synthesized but not compiled for simulation

I have written to the submitter to ask for the declarations of the two 
objects in
the case expression. I believe that they are constants of type either 
bit_vector or
std_logic_vector, in which case the interpretations are obvious.

Chuck Swart


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VHDL Issue Number:        2133 

Language_Version          VHDL-2002
Classification            LRM Examples, Notes and Appendices
Summary                   Not locally static expression is synthesized but not compiled for simulation

Relevant_LRM_Sections According to the LRM clause 8.8, the case
statement is required to have locally static expressions for
choices. When the expression is of an array type, the length of the
array must be known at compile time.
    
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              Andres Vazquez
Authors_Phone_Number      +4927398901160
Authors_Fax_Number        
Authors_Email_Address     vazquez@gdsys.de
Authors_Affiliation       
Authors_Address1          Dortmunder Strasse 4, 57234 Wilnsdorf
Authors_Address2          
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           24 June 2008
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

The following CASE expression:
    
    CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND 
    cREGADDRGeneralRangeMask) IS 
    
    leads to no problems when synthesizing it with
    Synplify Pro version 9.4L
    But when compiling it with ModelsimDesigner 6.3f
    an error message occurs:
    "...Array type case expression must be of a locally static subtype."
    So Synplify is not correct in their interpretation.
    

Proposed Resolution
-------------------



VASG-ISAC Analysis & Rationale
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TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
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TBD

VASG-ISAC Recommendation for Future Revisions
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TBD