VHDL Issue Number: 2006 Language_Version: VHDL-93 Classification: Language Modeling Enhancement or Deficiency Summary: "else" in "if generate"? Relevant_LRM_Sections: 9.7 Generate Statement Related_Issues: Key_Words_and_Phrases: generate statement, else Authors_Name: Allan Herriman Authors_Phone_Number: +61 3 9210 5527 Authors_Fax_Number: Authors_Email_Address: allan_herriman@agilent.com Authors_Affiliation: Agilent Technologies Authors_Address1: Authors_Address2: Authors_Address3: Current Status: Analyzed Superseded By: ------------------------ Date Submitted: 9 August 2000 Date Analyzed: 29-Oct-04 Author of Analysis: Peter Ashenden Revision Number: 1.1 Date Last Revised: 8-Nov-04 Description of Problem ---------------------- The "if - then" statement in VHDL has an "else" branch - but "if - generate" doesn't. It seems that every time I use this construct, I end up with: label_1: if condition_1 generate stuff_1; end generate; label_2: if not condition_1 generate stuff_2; end generate; This happens quite a lot in synthesisable code. (At least in the code that I write!) The idea being that I want exactly one of stuff_1 or stuff_2 to be synthesised. (Stuff_1 and stuff_2 would be different ways of implementing the same functionality - perhaps to get around compiler bugs, etc.) Obviously, an "else" would make this neater, and remove the possibility that my two conditions weren't quite complementary. (I guess this concept would extend to elsif as well.) Proposed Resolution ------------------- Proposed_Resolution: Add an "else" (and "elsif") to the generate statement. (not really a priority though) VASG-ISAC Analysis & Rationale ------------------------------ The VHDL-200x Modeling and Productivity group has placeholders for proposals for adding elsif/else clauses to if-generate statements and for case-generate statements. As of the date of this analysis, no work has been done in that group on preparing proposals. Currently, an if-generate statement has the form L : if condition generate declaration_list begin statement_list end generate; If the condition is true during elaboration, the statement is replaced with a block statement containing the declaration_list and statement_list. If the condition is false, the statement is replaced with nothing. An extension to allow elsif/else clauses would logically involve replacing the generate statement with nothing or a selection of one of a number of alternative block statements depending on the conditions. Since the content of each of the statement parts of the alternatives could be arbitrarily difference, it would seem appropriate to have separate declarative parts for each alternative, rather than sharing a single declarative part. Thus the abstract syntax of the extended statement would have - a first condition, along with an optional declarative part and a statement part - zero or more subsequent conditions, each with an optional declarative part and a statement part - an optional final unconditional alternative with an optional declarative part and a statement part The concrete syntax should subsume the existing syntax. An if-generate in the current form should appear as an extended generate in which there are no elsif or else alternatives. A possible concrete syntax might be L : if condition1 generate declaration_list begin statement_list elsif condition2 generate declaration_list begin statement_list ... else declaration_list begin statement_list end generate; An important aspect to this proposal is to consider how if-generate statements with elsif/else clauses would be configured in a configuration declaration. Currently, an if-generate of the form L : if condition generate ... end generate; is configured by a block configuration of the form for L ... end for; The contents of the block configuration are applied only if the condition is true. The structure of a block configuration would need to be extended to match the extended if-generate statement structure. Provision would need to be made to specify different configuration items for each of the alternatives in the if-generate statement. One possible approach would be to list configuration items for each alternative in the same order as the alternatives appear in the if-generate statement. Reserved words could be used to delimit the list of configuration items for each alternative, for example: for L ... elsif ... ... else ... end for; The structure of the block configuration would be required to correspond to that of the if-generate statement. If an alternative of the if-generate statement is elaborated, the corresponding part of the block configuration would apply. The VHDL-200x Modeling and Productivity proposal also calls for a case-generate statement. Again, the structure of such a statement would be syntactically analogous to the sequential case statement. A possible concrete syntax might be L : case static_expression generate when choices => declaration_list begin statement_list ... when others => declaration_list begin statement_list end generate; Similar considerations apply to configuring a case-generate statement. A possible approach would be to extend a block configuration to include alternative configuration items distinguished by choices: for L when choices => ... ... when others => ... end for; The proposed extensions would significantly enhance the usability of generate statements and should be developed as resources and effort permit. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- The VHDL-200x Modeling and Productivity group should pursue proposals for elsif/else clauses in if-generate statements and for case-generate statements, as resources and effort permit. -------------END OF IR----------------