VHDL Issue Number:      1081
Classification:         Language Definition Problem
Language Version:       VHDL-93
Summary:                Expression elaboration with impure functions
Related Issues:         1124
Relevant LRM Sections:  4.3.1,  5.1
Key Words and Phrases:  Expression, Attributes specification, generic map
Current Status:         Submitted
1076-1993 Disposition:  N/A
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1994/03/22
Author of Submission:   Anne Robert
Author's Affiliation:   LEDA S.A.
Author's Post Address:  35 Av du Granier 38240 MEYLAN FRANCE
Author's Phone Number:  (+33) 76 41 92 43
Author's Fax Number:    (+33) 76 41 92 44
Author's Net Address:   anne@leda.fr
-----------------------
Date Analyzed:          1997/07/22
Author of Analysis:     Peter Ashenden
Revision Number:        $Revision: 1.1 $
Date Last Revised:      $Date: 1995/07/25 18:37:19 $


Description of Problem
----------------------
With the use of impure functions, the order and the number of expression
evaluation become very important.
For an object declaration, a multiple object declaration is equivalent to a
sequence of single object declarations. Thus, the expression of the initial
valueÉ must be evaluated as many times as the number of object declarations.
+But an attribute specification, with a list of entity designators, applies to
the named entities denoted by the designator. The expression specifies the value
of this attribute for each of the named entities. Should the expression be
evaluated once or as many times as there are entity designators?
+The same questions exists for configuration specifications

Example :
architecture a of e
  shared variable v : integer := 0 ;
  impure function f return integer is
  begin
    v := v+1 ;
    return v ;
  end ;
  component comp1  end comp;
  component comp2 end comp;
  attribute att : integer ;
  signal s1, s2,s3,s4 : integer := f ;        -- Initial value of signal s1 : 1
  -- equivalent to :                          -- Initial value of signal s2 : 2
  --   signal s1 : integer := f;              -- Initial value of signal s3 : 3
  --   signal s2 : integer := f;              -- Initial value of signal s4 : 4
  --   É
  attribute att of s1,s2 : signal is f ;      -- Value of s1'att : 5 ?
                                              -- Value of s2'att : 5 ?
  attribute att of others : signal is f ;     -- Value of s3'att : 6 ?
                                              -- Value of s4'att : 6 ?
  for all : comp1 use entity work.ent generic map (f) ;
                       -- generic map of i1 : (7) ?
                       -- generic map of i2 : (7) ?
  for i3,i4 : comp2 use entity work.ent generic map (f) ;
                       -- generic map of i3 : (8) ?
                       -- generic map of i4 : (8) ?
begin
  i1 :  comp1 ;
  i2 :  comp1 ;
  i3 :  comp2 ;
  i4 :  comp2 ;
end;


Proposed Resolution
-------------------


VASG-ISAC Analysis & Rationale
------------------------------

LRM Section 12.3.2.1 describes elaboration of an attribute
specification.  It specifies that the expression is evaluated once,
and that the resulting value is used as the attribute value for each
of the named items.

Thus, in the issue author's example, s1'att and s2'att both have the
value 5, and s3'att and s4'att both have the value 6.

The second question is a question of when the expressions in the
binding indication are evaluated and in what order.  This is discussed
in ISAC IR1124.  The interpretation there is that the expressions in
the generic map of a binding indication are evaluated at the time of
elaboration of the inner block corresponding to the component
instantiation.  Hence, for a multiple configuration specification or
component configuration, the expressions in the generic map of the
binding indication are each evaluated once per component instance.
Where there are multiple association elements in the generic map, the
order of evaluation is undefined.

Thus, in the issue author's example, the actual generic constant
values for the component instances are:

	i1	 7
	i2	 8
	i3	 9
	i4	10


Thanks to those at the ISAC meeting of 2-Jul-1997 for contributing to
the resolution of this issue:

	John Willis
	Steve Bailey
	Greg Peterson
	Matthias Bauer



VASG-ISAC Recommendation for IEEE Std 1076-1993 
----------------------------------------------- 

No change.


VASG-ISAC Recommendation for Future Revisions 
--------------------------------------------- 

No change.