This is a request from the ISAC for input from the VHDL user community
to help resolve an issue of language definition.  The ISAC (Issues
Screening and Analysis Committee) is a subcommittee of the IEEE
Working Group responsible for developing and maintaining the Standard
VHDL Language Reference Manual.

Issue number 1117 relates to processes driving elements of resolved
composite signals.

Consider the following extract from a VHDL model:

  subtype byte is bit_vector(0 to 7);

  type byte_vector is array (natural range <>) of byte;

  function resolve_bytes ( drivers : in byte_vector ) return byte;

  signal s : resolve_bytes byte;

  ...

  p1 : process is
  begin
    s <= "00000000";
    wait;
  end process p1;

  p2 : process is
  begin
    s(0) <= '0';  s(1) <= '0';  s(2) <= '0';  s(3) <= '0';
    s(4) <= '0';  s(5) <= '0';  s(6) <= '0';  s(7) <= '0';
    wait;
  end process p2;

  p3 : process is  -- illegal
  begin
    s(0) <= '1';
    wait;
  end process p3;

In this model, the signal s is a composite resolved signal.  The
resolution function takes as its parameter an array of byte values and
returns a single byte value.  The processes p1 and p2 each have a
driver for each scalar subelement of s.

The process p3, however, only has a driver for one element of s.
According to the LRM as it currently stands, this is illegal.
(Section 4.3.1.2 lines 196-198 specify that a process that drives any
element of a resolved composite signal must drive all elements.
Section 12.6.1 lines 442-444 imply that the process p3 only has a
driver for s(0).)

A proposed change being considered by the ISAC would make the above
model legal.  The proposed change would involve defining drivers in a
process for all elements of a resolved composite signal if any scalar
subelement is assigned.  Such drivers would be created and initialized
in the normal way.  This involves creating an initial transaction for
each driver; the value of the transaction is the default value for the
signal.  If a process does not include an assignment for an element,
the value of the element remains the value of the initial transaction
on the driver for that element.

This behavior would be similar to the case of a process containing
assignments to a resolved composite signal in which the longest static
prefix of each assignment target is the whole signal.  For example,
consider the process:

  p4 : process is
  begin
    for i in 0 to 3 loop
      s(i) <= '1';
    end loop;
    wait;
  end process p4;

The longest static prefix of the target of the assignment is s.
Hence, Section 12.6.1 lines 442-444 imply that the process p4 has a
driver for each element of s.  All drivers have an initial transaction
with value '0'.  The drivers for s(0) to s(3) get an additional
transaction with value '1' from the assignement statement.  The
drivers for s(4) to s(7) get no further transactions, so maintain the
value '0'.

The advantage of the proposed change is that it allows a modeller to
write a process that modifies only some elements of a composite
resolved signal, without having to write assignment statements for all
of the remaining elements.

The disadvantage of the proposed change is that is removes the ability
of an analyzer to detect some errors of omission.  If the modeller
inadvertently omits assignments to some elements of a composite
resolved signal, the analyzer would infer drivers for those elements.

The ISAC seeks user input on whether the proposed change is desirable
or undesirable.  In particular, the committee would like to hear from
users who have had positive or negative experiences relating to this
aspect of the language.  More general comments relating to the issue
are also welcome.

Please forward your comments as soon as possible, but in any case by
August 26, to

	Peter Ashenden 

	Email: petera@ececs.uc.edu
	Fax:     +1 513 556 7326

	Dept ECECS
	University of Cincinnati
	PO Box 210030                                   
	Cincinnati OH 45221-0030, USA

Thanks in advance for your input.