VHDL Issue Number:        2116

Language_Version          VHDL-2002
Classification            Language Definition Problem
Summary                   What is the direction of std_logic_vector & '0'
Relevant_LRM_Sections     7.2.4
    
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              Larry
Authors_Phone_Number      Soule
Authors_Fax_Number        
Authors_Email_Address     larrys@synopsys.com
Authors_Affiliation       Synopsys
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           25 May 2007
Date Analyzed:		  11-Jul-2007
Author of Analysis:	  Peter Ashenden
Revision Number:          1
Date Last Revised:	  11-Jul-2007

Description of Problem
----------------------

The issue is with the code below
    
    signal S :
    std_logic_vector(6 downto 0);
    ...
    S & '0' ;
    
     
    
    What is the type of the expression "S & '0'"?  The table in
Section 7.2.4 says if the left operand type is "any one-dimensional
array type" and the right operand type is "the element type", then the
result type is "Same array type".  The way I read this is that the
result should be of the same type as S -- the left operand.  That is,
std_logic_vector with a downto range.  The other way to read it is
that the "same array type" is just std_logic_vector which defaults to
a "to" range.  However, B.15 defines "array type" as including the
index range.
     
    If it matters, this expression is then used as a parameter to a
function which takes an unconstrained array type: function f(inp :
std_logic_vector; size : integer), but I believe the input parameter
just inherits the bounds and direction of what was passed in.
    

Proposed Resolution
-------------------



VASG-ISAC Analysis & Rationale
------------------------------

The applicability of subprograms, including operators, is defined in
terms of parameter and result types, not subtypes. An array type
defines the index subtypes and the element subtype. However, it does
not define any index ranges; they are defined by constraints on an
array type that define an array subtype. These definitions are
specified in Clause 3.

In 7.2.4, the table specifies the parameter and result type profiles
of overloaded versions of the "&" operator defined for one-dimensional
array types. The rules for determining the index range of the result,
that is, the bounds and direction of the result, are specified in the
paragraphs following the table.

For the example quoted by the submitter, the type of the left operand
is STD_LOGIC_VECTOR. This is an unconstrained type, in which the index
subtype is NATURAL and the element subtype is STD_LOGIC. The table
specifies that the type of the result is the same type, namely,
STD_LOGIC_VECTOR.

To determine the index range of the result in the example, case b) of
7.2.4 applies. It specifies use of case a) with a non-null implicit
array formed from the element-typed operand. The rule of case a)
specifies the direction and bounds of the result. The index subtype of
the base type of the result is NATURAL, so the result has an ascending
range (since NATURAL is an ascending range) and has 0 (i.e.,
NATURAL'LEFT) as its left bound. The right bound follows from the
length of the result. Thus, the result of the example is an array of
type STD_LOGIC_VECTOR with an index range of 0 TO 7.

The submitter refers to Glossary item B.15, which, though informative
only, describes the term "array type." The wording is somewhat
imprecise, in that it describes an array type as "A type, the value of
which consists of elements that are all of the same subtype...". A type
does not have a value. Rather, is is a set of values. B.15 should more
precisely be "A type, each value of which consists of elements that
are all of the same subtype...". In the sequel, the index range in
which each index must lie is not a property of the array type, but of
a value that is a member of the array type.

The submitter also mentions that, further in the example, the resujlt
of the expression is used as an actual for a formal constant parameter
of type STD_LOGIC_VECTOR. The rules of 3.2.1.1 define the way in which
the formal parameter assumes the index range of the actual value in
this case.



VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

No change.