VHDL Issue Number:        2117

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Block comment is not there in vhdl
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              sudeep
Authors_Phone_Number      91-9911518886
Authors_Fax_Number        
Authors_Email_Address     sudeepts@gmail.com
Authors_Affiliation       
Authors_Address1          E-231, 1st floor, sec-27, Noida.
Authors_Address2          
Authors_Address3          

Current Status:           Submitted

Superseded By:

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Date Submitted:           29 May 2007
Date Analyzed:            02 August 2007
Author of Analysis:       Ajayharsh Varikat
Revision Number:          1
Date Last Revised:        02 August 2007

Description of Problem
----------------------

Please provide an option for block comment in vhdl-200 unlike in vhdl
there is only line comment, like other languages verilog, and vera,
vhdl should have block comments.

Proposed Resolution
-------------------



VASG-ISAC Analysis & Rationale
------------------------------

C-style delimited comments have been introduced in the 2006 Accellera revision of the VHDL standard. 


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

See ISAC analysis above.