Last Name First Name Affiliation VASG Voting Member IR2123 IR2124 IR2126 IR2127 IR2128 IR2129 LRM
Ashenden Peter Ashenden Designs Yes 1 1 1 1 1 1 1
Swart Chuck Mentor Graphics Yes A 1 1 1 1 1 1
Lewis Jim SynthWorks Yes 1 1 1 1 1 1 1
Molenkamp Bert University of Twente Yes 1[1] 1 1 1 1 1 1
Schneider Tim Synopsys Yes 1 1 1 1 1 1[2] 1
Shields John Mentor Graphics Yes 1 1 1 1 1 0 A
Ries John   Mentor Graphics Yes 0[3] 1 1 1 1 1 A
5 7 7 7 7 6 5
Varikat Ajayharsh Cadence Design Systems No 1 1 1 1 1 1 1
[1]
The proposed change corresponds with Note 1 (section 8.1 wait
statement)

The wait statement
wait until Clk = '1';

has semantics identical to

loop wait on Clk;
  exit when Clk = '1';
end loop;
[2]
Approve With Comment:  Null object accesses are difficult enough to debug when the tool points them out.  Removing such a check would make root cause analysis of a crash/core dump extremely difficult.  Vote to approve the VASG-ISAC recommendation for 'no change'.
     
(BTW, System Verilog also points out null object access, although the context I'm referring to is a bit different than this specific case)
[3]
I think the standard should specify one point or the other. Otherwise
the user of this callback can't
assume one way or the other and there is no simple way to get the other
functionality.
My preference is the call back should occur only if the wait condition
is true.