Subject: RE: Synchronization with SystemVerilog 3.1A
From: Bailey, Brian (brian_bailey@mentorg.com)
Date: Tue Jun 17 2003 - 12:28:19 PDT
Hi Andy,
I think there are a number of ways to address this. As an Accellera chair, I have been given orders from my boss. He doesn't pay the bills, but somehow I get his love from this. Now I know we don't always do what the boss says, but you have to have very good reasons based on sound technical arguments to succeed. We will have to discuss this possibility and see if we do indeed have the necessary ammunition.
The second way to look at this is that I agree, we need to remain neutral because there is still a lot of VHDL out there, so as a minimum we need something compatible with both of those and possibly others. I don't much care if we require fairly thing wrappers around a neutral API to get into these environments or any others. What would be important is that we ensure that they can be connected or used together. In addition, we know that the current interface as defined in SystemVerilog is not sufficient for our needs, so we either need to work with them to come up with extensions that do satisfy all of our requirements, or we have to extend what is there and then try and push those extensions into SystemVerilog. Again, I think this is something that we need to discuss.
Either way, I think we as a committee have to decide on the best path and then to execute on it.
-----Original Message-----
From: Andy Eliopoulos [mailto:andye@cadence.com]
Sent: Tuesday, June 17, 2003 11:37 AM
To: Bailey, Brian; itc@eda.org
Cc: Brophy, Dennis
Subject: RE: Synchronization with SystemVerilog 3.1A
Brian,
Do we really need to go down the path of SystemVerilog
v. IEEE Verilog 1364-2005, or should this committee
continue to develop a neutral API?
Andy Eliopoulos
Cadence
> -----Original Message-----
> From: Bailey, Brian [mailto:brian_bailey@mentorg.com]
> Sent: Tuesday, June 17, 2003 11:18 AM
> To: 'itc@eda.org'
> Cc: Brophy, Dennis
> Subject: FW: Synchronization with SystemVerilog 3.1A
>
>
> Hi Guys,
> We have some marching order from our boss, that we have
> to look at ensuring the SCE-API is compatible with
> SystemVerilog by February 2004. That means that we have to
> get started on looking at what problems we may have and the
> steps that we need to take.
> Since I didn't hear any comments about my last posting,
> or about the proposed date for the next meeting, then I will
> set it to be: Thursday 26th June at 9:00 PST.
>
> Call in details
> 888 742 8686
> Intl 303 928 2600
> Conf ID 4252566
>
> Agenda Items
> Donation procedures and process
> Workshop planning
> SCE-API and SystemVerilog
> Any other business
>
>
> -----Original Message-----
> From: Vassilios.Gerousis@infineon.com
> [mailto:Vassilios.Gerousis@infineon.com]
> Sent: Tuesday, June
> 17, 2003 6:58 AM
> To: srikanth.chandrasekaran@motorola.com; Bailey, Brian
> Cc: david.smith@Synopsys.COM; fhaque@cisco.com;
> Ghassan.Khoory@Synopsys.COM; Karen.Pieper@Synopsys.COM;
> Stephen.Meier@Synopsys.COM; mittra@juno.com;
> johny.srouji@intel.com; Ghassan.Khoory@Synopsys.COM
> Subject: Synchronization with SystemVerilog 3.1A
>
>
> As part of my announcement on SystemVerilog 3.1A (to be
> completed by DVCON 2004), I have added synchronization with
> Verilog-AMS and also SCE-API.
>
> We are proceeding on a set of milestones for
> SystemVerilog. This includes support of synchronization of
> the three standards. Without these synchronization we cannot
> go to IEEE. Here what I expect at minimum:
>
> 1- Verilog-AMS should at least use the SystemVerilog 3.1 BNF
> (to be modified for 3.1A). The BNF is available of
> SystemVerilog 3.1 is available for use. This is based on IEEE
> 2001 Verilog.
>
> 2- Verilog-AMS could use some of the new data types like
> real, etc. It could also examine the use of interfaces as
> mechanism of adding an analog macro to a SystemVerilog. It
> can also inherit some of the Testbench capabilities and
> possibly assertions.
>
> 3- In terms of SCE-API, we talked about separating the
> current SCE-API into three parts. One of them could be the
> C-interface defined for SV 3.1. We can also start the
> emulation acceleration and see what that can bring to both committees.
>
> Let me know what your thoughts are.
>
> Best Regards
>
> Vassilios
>
>
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