notes

Notes from Accelera ITC meeting 2004/10/14

IM05
Per suggests that the enabled signals could be shown longer in
the diagram. There was some discussion. Duaine thinks that
the enable signals should be guaranteed valid only on the
corresponding edge, with no duration after.
Per suggests that we should simplify the clock control with
only one control signal per clock, no separate pos-edge and
neg-edge. Once the rfcclk is deasserted, on the next rising
edge of uclock time is stopped. We need clarification as to
what is the difference between that and the emergency break.
He want to see justification for separte pe and ne control in
the emergency brake model context.

AI - Per and John to clarify choices by the next meeting
AI - Brian update status of IM05 on website.

We need a clarification in the spec that the amount of wall
clock or the number of uclocks between cclocks is not
specificed. What is specified is the order of controlled
clock edges of clocks sourced by clock ports.

AI - Duaine and Brian - Insert clarification text in the
appropriate portion of spect.

IM13
AI - Duaine to write up global order from HW to SW, single
order from SW to HW.

IM18
Abandoned due to change in halt semantics.

Uncatalogued issues

Per will create a collection of uncatalogued issues by
10/21/2004 to evaluate.

IM23
AI - Duaine and Brian make sure that is in the spec and update
the status

IM24
AI - Duaine and Brian to make sure it is in the spec and
update status.

IM25
AI - Duaine and Brian to make sure that Johns proposal made it
into the spec and update the status.
We agreed to a note to be included. It appears in 5.4.2.2.

IM08 and 09
AI - Duaine and Brian to be sure that port priorities are out
of the existing document. In section 5.2.3.1 refers to an
outdated port priority. Parameter will stay and be
deprecated.
Received on Thu Oct 14 10:05:57 2004