Message from John Stickley on IM05

        John’s message was too large for the reflector, so I am splitting it
up. Diagram each in a separate email.
        Brian
        
        
        ITC Team,
        I've attached two new diagrams for the IM05 clock forms.
        In the first diagram (revised_clock_control_1.jpg) it is
        simply what I had before but with added reference lines so
        it is easier to see where clocks align around the
        'ready_for_clk*' signal transitions.
        In the second diagram  (revised_clock_control_2.jpg), I've
        implemented Per's request of showing assertions of
        'clk*enabled' signals on posedges of uclock rather than
        negedges to avoid possibly misleading implementors. As it
        turns out, either is acceptable and compliant.
        The important thing is that a 'clk*enabled' signal
        can be sampled properly on the relevant posedge of a uclock.
        I elaborate on this a bit more in specific responses
        to Per's e-mail below.
        Please let me know which of the two you would prefer
        for the specification.
        Brian please let me know if the reflector does not take this.
        I'll send you .fm versions privately.
        -- johnS
               
               
               
Received on Tue Nov 9 14:30:57 2004