OM05: additional explanatory text for clock control waveform diagrams

Team,

I've added explantory text for my waveform diagrams as discussed
in the last meeting.

Recall the decision was to go with diagram 2 to but to add clarification
text about what uclock edges "clock enabled" assertions can occur on.

I added additional overall explanatory text for the diagram as well.

I'm still working on the revisions to the diagram that will illustrate
"just-in-time" clock control semantics as well as proposed
specification revisions for the same.

But in the meantime this text is ready for review.

I will forward the Frame doc. to Brian so he can easily incorporate
it if all meets with everyone's approval.

I've included this text as a text e-mail so we don't have reflector
size limit issues.

Once I have the modified waveforms, I'll send the .pdf with everything
in it.

Added text:
------------------------------- snip --------------------------------

Figure X shows an example of clock control for two fast clocks (clkfast,
clkfast_negedge) that use don’t care duty cycle semantics and one slow
clock (clkslow) that uses a 50/50 duty cycle. clkfast uses posedge active
don’t care duty cycle and clkfast_negedge uses negedge active
don’t care duty cycle.

The effect of the 4 respective clock control signals ready_for_clkfast,
ready_for_clkfast_negedge, ready_for_clk_slow, and ready_for_clk_slow_negedge
can be seen.

Deassertion of ready_for_clkfast prevents subsequent posedges of clkfast,
negedges of clkfast_enabled, and all edges of clk_slow from occuring on
subsequent posedges of uclock. Once re-asserted, all these edges are
allowed to occur on the subsequent uclock posedge.

Deassertion of ready_for_clkfast_negedge prevents subsequent posedges of
clkfast, negedges of clkfast_enabled, and all edges of clk_slow from occuring
on subsequent posedges of uclock. Once re-asserted, all these edges are
allowed to occur on the subsequent uclock posedge where relevant.

Note, that all of the clock enabled signals, clkfast_enabled,
clkfast_negedge_enabled, clkslow_enabled, and clkslow_negedge_enabled
are shown to transition on uclock posedges. The implementation can also
choose to transition them on negedges. The only hard requirement is that
their values can be sampled on the uclock posedge at which the associated
controlled clock edge will occur.

-- johnS

______________________________/\/ \ \
John Stickley \ \ \
Principal Engineer \ \________________
Mentor Graphics - MED \_
17 E. Cedar Place \ john_stickley@mentor.com
Ramsey, NJ 07446 \ Phone: (201) 818-2585
________________________________________________________________
Received on Thu Nov 18 09:16:30 2004