Hi Brian, I would like to add that another interest of recording the calls is in term of complete understanding of the discussion especially for the non-native english speakers. An authentificated access for the download could be setup to better take into account the participation to the activity regarding new voting rules. Scemi 2.0 is to be considered as an extension of scemi 1.1 which aims to facilitate the use and the development of co-emulation transactional interfaces. The key points seen to keep coherency with scemi 1.1: - in term of compatibility and evolution: * Ability to easily reuse all the scemi 1.1 transactors and the C++ API in combination with the new "transactors/function calls" and the new SW API. * The new SW API must not imply the use of SV/DPIO: => an (efficient) C++ (or C) API is mandatory (and find a way to cope with scope management if necessary) * The new transactors "transactors/function calls" need to be defined and exist in both typical languages as VHDL and Verilog. - in term of performances and use model: * Having two level of running modes: ** One which is determinist (essential for an efficient debug) ** One which may not be determinist (on cycle base) but aiming at speed performances and for which concurrent execution on HW and SW side are certainly the key points for optimizing the impact of synchronization. * Preserving scemi 1.1 compatibility as it allows to use the uclock which is free running: ** It allows to interface with an external target taking into account real-time issue ** It allows to perform complex message generation or processing within an undefined number of DUV clock cycles. Best regards, Joseph Bulone -----Original Message----- From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf Of Brian Bailey Sent: Tuesday, July 12, 2005 6:04 PM To: itc@eda.org Subject: FW: Meeting Minutes From: Michael Frank BENJAMIN [mailto:mike.benjamin@st.com] Sent: Monday, July 11, 2005 9:16 AM To: brian_bailey@acm.org Cc: Mike Benjamin; Joseph Bulone (Joseph Bulone) Subject: RE: Meeting Minutes Hi Brian, Meeting time works quite well for me as this in end of working day in UK. Not so good for France/rest of Europe where they are 1 hour ahead. Recorded calls would certainly be usefull. I am trying to attend meetings to get up to speed on the discussion but for example next Thursday I will be flying to Italy and so will miss the scheduled meeting. I have 2 specific issues that I would like addressed by SCE-MI 2.0. These are requirements rather than implementation issues as I am approaching this as a customer. Hopefully members of the committee will come up with good ways of adapting the Mentor proposal to satisfy these 'user' issues: 1) Backwards compatability with SCE-MI 1.1, possibly through adaption/wrapper ie: easy migration path for existing users. ST is already doing a lot with SCE-MI and we do not want to have to throw this away in order to move to SCE-MI 2.0 3) Consistent support for VHDL, Verilog and SystermVerilog. I hope this is adequately addressed by the discussion of a "functional call interface available in each language" Joseph Bulone (who manages my emulation team) will send a list of more specific issues eg: impact of limiting clock control. Regards, Mike Benajmin STMicroelectronics, Mail: 1000 Aztec West, Bristol BS32 4SQ, UK Email: mike.benjamin@st.com Phone: +44 1454 462469 Fax: +44 1454 462305 Mobile: +44 7768 025437 > -----Original Message----- > From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf > Of Brian Bailey > Sent: 30 June 2005 18:35 > To: itc@eda.org > Subject: Meeting Minutes > > > Here are the minutes from today's meeting. I would be > very interested in hearing from our Asian and European > members about ideas for making the committee more accessible > to them. Would recorded calls be useful? Would you listen to > them? Are there other things that we could do to help you? > > Thanks for any input > Brian. > >Received on Thu Jul 14 08:15:12 2005
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