Re: one SystemVerilog inconsistency cleared up

Hi John,

> So basically any SV integer type can have a post qualifier 'unsigned'
> that makes it unsigned. That would map to the corresponding unsigned
> type in C.
>
> For example 'byte' denotes a signed 8 bit integer that maps to 'char'.
> But 'byte unsigned' denotes an unsigned 8 bit integer that maps
> to 'unsigned char'.

Ok, that makes much more sense!  But why did they choose to make
`unsigned' a post qualifier and not a pre qualifier as in C? :-(
Probably constraints imposed by the language grammar . . .

What about the question of defining types on the C/C++ side of
DPI that matches the Verilog integer types, e.g.:

  typedef sv_byte <8 bit signed integer type>;
  typedef sv_byte_unsigned <8 bit unsigned integer type>;
  typedef sv_shortint <16 bit signed integer type>;

etc.  Does SystemVerilog/DPI have this or is this an area where
we can propose an improvement?  I'd like to at least find out
if this was considered and whether it was decided against doing
this, and if that is the case, why?

Thanks,
Per

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
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