RE: HDL Support (was RE: Meeting minutes 050825)

Just curious, did SCEMI 1.1 compliance mandate supporting both
VHDL and Verilog?  As a user who's tested several different
SCEMI 1.1 products, I never bothered to ask if they had VHDL
support since we are almost exclusively a Verilog house. It
wouldn't occur to me to protest if I was marketed a product
that was "SCEMI 1.1 compliant, verilog only" (or VHDL only
if we were a VHDL house). Same goes for SCEMI 2.0.

I'm not trying to advocate anything here, just a user's perspective.

---------------------------------------
---    Russ Vreeland (949)926-6143  ---
---    vreeland@broadcom.com        ---
---    Senior Principal Engineer    ---
---    Broadcom Corporation         ---
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> -----Original Message-----
> From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf 
> Of Shabtay Matalon
> Sent: Thursday, September 15, 2005 2:23 PM
> To: bojsen@zaiqtech.com
> Cc: vreeland@broadcom.com; John Stickley; itc@eda.org
> Subject: RE: HDL Support (was RE: Meeting minutes 050825)
> 
> 
> Per,
> 
> SCE-MI 2.0 compliance should mean supporting all the 3 
> languages (SystemVerilog, VHDL or Verilog 2001). We should 
> not support the concept of building SCE-MI 2.0 as 
> SystemVerilog only standard or define SCE-MI 2.0 compliance 
> in the domain of only one language (SystemVerilog for example).
> 
> This should not preclude us from working the issues in each 
> language a step at a time. We can address each issue for the 
> 3 language at the same time or work one language at a time 
> and reconcile as deems logical to us as a group.
> 
> I will not get into C vs. C++ at this time as this may need 
> more thought and discussion.
> 
> Shabtay 
> 
> >-----Original Message-----
> >From: Per Bojsen [mailto:bojsen@zaiqtech.com]
> >Sent: Thursday, September 15, 2005 1:30 PM
> >To: Shabtay Matalon
> >Cc: vreeland@broadcom.com; John Stickley; itc@eda.org
> >Subject: HDL Support (was RE: Meeting minutes 050825)
> >
> >> We at Cadence believe that the decision which language to 
> use for DUT 
> >> and BFM modeling (SystemVerilog, VHDL or Verilog 2001) 
> should be made
> by
> >> our customers and that a SCE-MI 2.0 standard should respect this 
> >> assumption and provide a solution that does not compromise 
> the needs
> of
> >> any of the SystemVerilog, Verilog 2001 and the VHDL communities.
> >
> >This leads to the following question: For a SCE-MI 
> implementation to be 
> >considered compliant must it support all languages supported by the 
> >standard, or is there a concept of a compliant SystemVerilog 
> >implementation, etc.? This of course also extends to C versus C++ 
> >support.
> >
> >Per
> >
> >--
> >Per Bojsen                                Email: 
> <bojsen@zaiqtech.com>
> >Zaiq Technologies, Inc.                   WWW:
> http://www.zaiqtech.com
> >78 Dragon Ct.                             Tel:   781 721 8229
> >Woburn, MA 01801                          Fax:   781 932 7488
> >
> >
> 
> 
>