Hi John, After looking at your revised proposal, we yet don't see how it addresses the language support issue on standard IEEE compliant simulators. Let's assume for now that a. Verilog and VHDL simulators can compile the code with the attributes. b. The attributes can be extracted by VPI using standard attribute query calls. Now the attributes needs to be interpreted by the simulators in some meaningful way. Does this regeneration require the modification of the original code? Can you run the original code on standard VHDL and Verilog 2001 simulators by linking in a library w/o modifying the original code? By our analysis, you are suggesting that the Infrastructure Linker conduct complete code regeneration. In addition, it is not clear at all how you would call Verilog/VHDL from C because (for example when implementing a DPI export function) as such call is beyond the scope of standard PLI/VHPI. Can you explain again how you would do that in pure simulation mode? Last meeting's summary (before the face to face) contained the following section: "Russ asked for an example of how the 2.0 interface would work in a pure simulation environment. Function calls with attributes. Need a feasibility study to show it is possible to implement. John and Duaine will consider the amount of work necessary to do this." I believe that w/o addressing this requirement and illustrating how your proposal would work in pure simulation using standard means in Verilog 2001 and VHDL, and illustrating a flow that does not conduct code regeneration, your latest attribute based proposal does not address the language issue. Thanks, Shabtay >-----Original Message----- >From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf Of John >Stickley >Sent: Tuesday, September 20, 2005 5:59 AM >To: 'itc@eda.org' >Subject: Proposed changes for attributes replacing pragmas for DPI >import/export declarations > >Greetings ITC Techies, > >As per my AI, here is a re-write of section 3.2.1 of the >Mentor SCE-MI 2 proposal to replace pragma syntax for >DPI import/export declarations with a string attribute >syntax that can be used both for Verilog 2001 and VHDL. > > >3.2.1 Attribute syntax adaptation >For SCE-MI 2, we will want to retain the look and feel of the DPI HDL layer >but with a special adaptation for Verilog and VHDL since part of the SCE-MI >requirements is for the API to be multilingual and require no language >syntax >extensions. As described in the previous section, the import and export >declarations in SystemVerilog are part of the language syntax. Because >these >syntax extensions do not exist for Verilog or VHDL, another mechanism must >be >deployed to declare functions as imported or exported. > >For both Verilog and VHDL it is proposed to use a attribute syntax for this >purpose. A attribute can be used to alert infrastructure compilers that >they >are expected to interpret the value of the attribute and make any special >adjustments necessary to implement bindings to the imported or exported >functions. > >Both Verilog 2001 and VHDL allow attachment of attributes to function >declarations. In the proposed scheme, the attribute values will be >string types the follow a syntax similar to the import/export syntax >of SystemVerilog. > >Figure 5 shows Verilog and VHDL attribute syntax compared to SystemVerilog >native syntax used when declaring an imported function. For VHDL 1992, >since the FOREIGN attribute is part of package STD, we can easily make >use of it to attribute DPI functions in the manner shown. > >----------------------------------------------------------------------- ---- >---- >Figure 5: Attribute syntax to declare imported DPI function in Verilog and >VHDL > >SystemVerilog Import Declaration >-------------------------------- >[unchanged] > >Verilog Import Declaration >-------------------------- >(* sce_mi="import DPI-C" *) >function nb_put; > input ttype; > input status; > input [`DATA_WIDTH-1:0] d; > begin end // Empty function >endfunction > >VHDL Import Declaration >----------------------- >function nb_put( > ttype: std_logic; > status: std_logic; > d: std_logic_vector(DATA_WIDTH-1 downto 0)) > return std_logic is >begin end -- Empty function > >attribute foreign of nb_put: function is "sce_mi import DPI-C"; > > >In both the Verilog and VHDL cases, an empty "place-holder" function is >used to represent the imported function. It is shown with the string >attribute >that alerts the infrastructure compiler that this function represents a >foreign >function that is actually defined on the C side. > >Figure 6 shows Verilog and VHDL attribute syntax compared to SystemVerilog >native >syntax used when declaring an exported function. > >----------------------------------------------------------------------- ---- >---- >Figure 6: Attribute syntax to declare exported DPI function in Verilog and >VHDL > >SystemVerilog Export Declaration >-------------------------------- >[unchanged] > >Verilog Export Declaration >-------------------------- >(* sce_mi="export DPI-C" *) >function configQuery; > input enableParity; > begin > isParityEnabled = enableParity; > configQuery = currentState; > end >endfunction > >VHDL Export Declaration >----------------------- >function configQuery( > enableParity: std_logic ) > return std_logic_vector(7 downto 0) is >begin > isParityEnabled := enableParity; > return currentState; >end > >attribute foreign of configQuery: function is "sce_mi export DPI-C"; > >For exported functions, in the SystemVerilog, Verilog, and VHDL cases >the function body is declared in a similar way (actually identically >in Verilog since it is a subset of SystemVerilog). But in SystemVerilog >an additional export declaration designates this function as callable >from the C side. Whereas in Verilog and VHDL again, a string attribute >is used. > >Note: For VHDL, forward declarations can be used as well such that >the forward declaration can be followed by an attribute declaration >and that can be separate from the exported function definition itself. > >-- johnS > >______________________________/\/ \ \ >John Stickley \ \ \ >Mgr., Acceleration Methodologies \ \________________ >Mentor Graphics - MED \_Received on Fri Sep 23 10:09:35 2005
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