Action Item: Draft proposal for prevention of SCE-MI 1.1 and SCE-MI 2.0 model mixing

Greetings ITC Techies,

One of my AI's last week at the face to face was to write up
a formal requirement for preventing mixes of SCE-MI 1.1 constructs
with SCE-MI 2 constructs in the same transactor and C models.

For purposes of this description, the following definitions
are given:

A SCE-MI 1.1 HDL model is defined as a hierarchy with
the following properties:

1. At least one SCE-MI 1.1 message port or clock control macro
    (but not clock port macro) is instantiated at the highest
    level of the hierarchy within the model.

2. More SCE-MI 1.1 message ports or clock controls may be
    instantiated at lower sub-hierarcies of the model.

A SCE-MI 2.0 HDL model is defined as a hierarchy with
the following properties:

1. At least one SCE-MI 2.0 DPI function call us declared
    at the highest level of the hierarchy within the model.

2. More SCE-MI 2.0 DPI function calls may be declared at
    lower sub-hierarchies of the model.

Requirements for SCE-MI 2:
1. No SCE-MI 1.1 models as defined above can contain any
    SCE-MI 2.0 function call declarations or calls anywhere
    in their hierarchy.

2. No SCE-MI 2.0 models as defined above can contain
    any SCE-MI 1.1 message port or clock control macros
    anywhere in their hierarchy.

3. No SCE-MI 1.1 callback functions can make direct calls
    to exported DPI calls.

4. No SCE-MI 1.2 imported function calls can make calls
    to the SCE-MI 1.1 service loop or to send on any of
    the input ports.

-- johnS


______________________________/\/            \     \
John Stickley                   \             \     \
Mgr., Acceleration Methodologies \             \________________
Mentor Graphics - MED             \_
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