RE: supporting DPI in VHDL - possible scenarios for implementation

Hi Russ,

 

Please see my notes bellow.

 

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I suspect it was a mistake to try to resolve this issue at this time.
The other issues which are pertinent to the SystemVerilog case ought to

be tackled first, then we can come back to VHDL and Verilog2001. The
great technical advancement of SCEMI 2.0 is (using SystemVerilog) we can
achieve a testbench methodology truly portable from simulation to
emulation. We should solve remaining SystemVerilog issues without
distraction. Then, this optimal solution will help us figure out the
(necessarily) less optimal solution for the other simulators. 

 

What does the rest of the committee think? Is it time to table this
issue lest we spend the rest of the time available for technical
discussions on it? Perhaps given the time constraints, this is a SCEMI
2.1 issue.

[Shabtay] I actually agree with you assessment. Great part of the
discussion and many of the emails going back and forth were trying to
"retrofit" the existing DPI-based proposal into Verilog 2001 and VHDL. I
think it will be a clean solution if we focus on resolving first the
remaining SystemVerilog issues in SCE-MI 2.0 and deal with any changes
to Verilog 1001 and VHDL after SCE-MI 2.0 gets approved and SCE-MI 2.1
gets discussed. We all agreed that SCE-MI 1.1 will be supported in
SCE-MI 2.0 and we have agreed to support a coexistence use model of
SCE-MI 1.1 macros in SCE-MI 2.0. Correct?

 

If all members agree to this, let's pull all Verilog 2001 and VHDL
related proposals off the table. Each ITC member (now and in the future)
could bring any proposal they wish post SCE-MI 2.0 approval for SCE-MI
2.1. What do you think?

 

We also have been holding on officially bringing our macro based
proposal now to the committee in spite of the fact that these macros
meet all principles stated across the three HDLs with the only exception
that these are not function-based on the HW side. We also stated our
support for SCE-MI 2.0 to be DPI-based standard for SystemVerilog. 

 

The one principle that they do not meet is the furtherance of  portable
IP written for both simulation and emulation. Also, if you say you
support

SCEMI2.0 to be DPI-based for SystemVerilog, then why state that the
macros meet all principles for SystemVerilog (one of the 3 HDLs).?

[Shabtay] I hope that the above (if accepted) will put the Verilog 2001
and VHDL issue to bed for now. But from a pure technical perspective,
the macros based approach that Cadence has proposed in the past (not
SCE-MI 1.1 macros to be clear), does meet all principles including
supporting congruent use model with simulation. The only caveat is that
it is not function-based on the HW side (or DPI-based) as the committee
desires for SystemVerilog.

 

Thanks,

 

Shabtay

 

 

Cordially,

Russ

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---   Russ Vreeland (949)926-6143  ---
---    vreeland@broadcom.com <mailto:vreeland@broadcom.com>         ---
---    Senior Principal Engineer    ---
---    Broadcom Corporation         ---
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