RE: supporting DPI in VHDL - possible scenarios for implementation

Hi Russ,

 

While we prefer to deal with Verilog and VHDL as a SCE-MI 2.1 topic,
Cadence is willing to accept your proposal as stated below as a
compromise.

 

Regards,

 

Shabtay

 

 

________________________________

From: Russell Vreeland [mailto:vreeland@broadcom.com] 
Sent: Wednesday, October 12, 2005 4:36 PM
To: Shabtay Matalon; bojsen@zaiqtech.com; itc@eda.org
Subject: RE: supporting DPI in VHDL - possible scenarios for
implementation

 

What I proposed was that we table discussions of Verilog 2001 and VHDL
with regard to SCEMI 2.0 until we complete the gist of the specification
for SystemVerilog.  If it turns out that time doesn't permit revisiting
the question before our deadline arrives, then it could possibly be a
SCEMI 2.1 topic if the spec continues to evolve.