Hi Per, Just few notes below. I am not avoiding your comments on unified API on the software side. These are all valuable points to look at, but not at this time. Regards, Shabtay > >Well, there is no fluidity in regards to the software interface. >It is DPI. [Shabtay] If this was just DPI, we would not be dealing for so many weeks with data types and state support. The fluidity is in what we will end up supporting out of the entire DPI spec on the SW side in SCE-MI 2.0. > >Shabtay> My data is somewhat different. I think that it is yet to be >Shabtay> seen what IP vendors will prefer to choose. > > >Shabtay> End users, if these are not IP developers, are quite shielded >Shabtay> from the interface used inside the transactors. I am not sure I >Shabtay> understand your point here. > >End users of SCE-MI implementations that are not IP developers >but that also develop transactors. This is quite common, of course. >They have different goals than IP developers but they still have >to write transactors. [Shabtay] OK, I understand what you intended to say. I went by the definition of the 'end user' as one that relies on transactor implementor to provide the IP, thus doesn't need to be involved with the internals of the IP. I have no issue with your clarified definition. > >Shabtay> the best solution I believe we should pursue at this time >Shabtay> is to work on SystemVerilog first, release this work in >Shabtay> SCE-MI 2.0 as soon as possible and evaluate how customers >Shabtay> would be receptive to it. > >We have general consensus to focus on SystemVerilog in our >discussions at the meetings for now. So far so good. > >Shabtay> We should defer the issue of >Shabtay> functional API for Verilog and VHDL to SCE-MI 2.1 time >Shabtay> frame and bring the most viable solutions to the table at >Shabtay> that time. > >This is still a point of contention. The committee has not made >this decision yet and there is certainly not consensus on this >issue yet. Your proposal essentially makes SCE-MI 2.0 a SystemVerilog >only standard and leaves Verilog and VHDL at SCE-MI 1.1. [Shabtay] Please see my responses to Russ and Brian Bailey (I won't repeat it here). I agreed with both of them. I hope (but not sure) that this will gain a board consensus. Since this >is what Cadence wants, why don't you just choose not to implement >the proposed function based interface for Verilog and VHDL and >let the rest of us do it? [Shabtay] This is not a viable option for us. The language issue with Verilog and VHDL is a fundamental issue. Either we endorse the SCE-MI 2.0 standard in it entirety or we don't. I think this is time to end to this email trail and move on to focus on SystemVerilog only issues for now. > >Per > >-- >Per Bojsen Email: <bojsen@zaiqtech.com> >Zaiq Technologies, Inc. WWW: http://www.zaiqtech.com >78 Dragon Ct. Tel: 781 721 8229 >Woburn, MA 01801 Fax: 781 932 7488 >Received on Wed Oct 26 17:01:36 2005
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