Re: time access proposal

Hi All:

Please see my comment on the verilog header for SceMiClockPortP below:

John Stickley wrote:
> Greetings ITC Techies,
> 
> Here's the AI from Russ and myself for time access. It is mainly
> a writeup of the proposal we discussed verbally last meeting
> and, I think, got more of less of a consensus on.
> 
> Proposal:
> 
> ----------------------------------------------------------
> Part 1: C-Side Time Access
> 
...
> ----------------------------------------------------------
> Part 2: Establishing Time Base on H/W side
> 
> Currently in the SCE-MI 1.1 specification, since all clock
> definitions are ratio based, there is no way of specifying the
> time base on the H/W side.
> 
> In order for to be able to implement time accesses from the C
> side (as described in Part I above), there must be a way of
> fixing the H/W side time base.
> 
> The easiest way to do this is to specify the period of at least
> the fastest user cclock. By doing this, the cyclestamp can
> be associated directly with actual absolute time units.
> 
> Do do this, we propose a variant of the SceMiClockPort macro that
> allows specification of a clock period. This new form of the macro
> is called SceMiClockPortP defined as follows:
> 
> 
>     module SceMiClockPortP( Cclock, Creset );
>         parameter ClockNum=1;
>         parameter ClockPeriod = "1 ps";
>         parameter DutyHi=0, DutyLo=100, Phase=0;
>         parameter ResetCycles=8;
>         output Cclock, Creset;
>     endmodule
> 
...

> The clock period specification is given as a string which will
> be parsed by the infrastructure to establish the period
> of that clock.
> 
> The default period shall be 1 ps. Notice that the period
> specification replaces the ratio specification in the
> current SceMiClockPort macro.
...

I would propose that the ClockPeriod be specified with explicit time units and not be encoded in 
strings so that it is trivial to write the verilog to implement the module;

There are two alternate options i can think of; i prefer proposal 2 because it is closer to being 
useable.

proposal 1:

         parameter time ClockPeriod = 1ps;

To my reading of P1800_D6 the above is legal System Verilog; however, popular sysv implementations 
error out at present on 'ps'. I will file bugs.

proposal 2:

The alternate below is parsed by one sysv implementation and is an error on another.

     module SceMiClockPortP( Cclock, Creset );
	timeunit 1ps;
	timeprecision 1ps;

	parameter ClockPeriod = 1;

-- 
regards,
Ramesh