Hi, > Now, what happens with the second message? If the transactor does > not assert ReceiveReady the message cannot be sent to the port since > the first message is still waiting to be transferred. Hence, the > first while loop will loop forever or at least until the transactor > decides to assert ReceiveReady, that is we have a deadlock. I forgot to mention that I am assuming that the HW side infrastructure only has room for one input message per input port. If it has room for n messages we can extend the argument to n+1 messages. The deadlock is still possible if I'm interpreting the pseudo code correctly. To my knowledge SCE-MI does not impose any requirements on the number of messages the HW infrastructure is supposed to buffer so assuming a buffer depth of 1 message is perfectly reasonable, right? Per -- Per Bojsen Email: <bojsen@zaiqtech.com> Zaiq Technologies, Inc. WWW: http://www.zaiqtech.com 78 Dragon Ct. Tel: 781 721 8229 Woburn, MA 01801 Fax: 781 932 7488Received on Thu Mar 23 05:57:08 2006
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